ISL97650ARTZ-T Intersil, ISL97650ARTZ-T Datasheet - Page 18

IC LCD SUPPLY HP 4CHN 36-TQFN

ISL97650ARTZ-T

Manufacturer Part Number
ISL97650ARTZ-T
Description
IC LCD SUPPLY HP 4CHN 36-TQFN
Manufacturer
Intersil
Datasheet

Specifications of ISL97650ARTZ-T

Applications
LCD TV/Monitor
Current - Supply
250µA
Voltage - Supply
4 V ~ 14 V
Operating Temperature
-40°C ~ 105°C
Mounting Type
Surface Mount
Package / Case
36-TQFN
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ISL97650ARTZ-T
Manufacturer:
INTERSIL
Quantity:
20 000
delay the output until the boost is enabled internally. The
delayed output appears at A
A
soft-start ramp depends on the value of the C
For C
time, DELB gate goes low to turn on the external PMOS to
generate a delayed A
V
Once the start-up sequence is complete, the voltage on the
C
detected or the EN pin is disabled. If a fault is detected, the
voltage on C
disabled until the power is cycled or enable is toggled.
A
DELB pin is an open drain internal N-FET output used to
drive an external optional P-FET to provide a delayed A
supply which also has no initial pedistal voltage (see
Figure 14 and compare the A
curves). When the part is enabled, the N-FET is held off until
C
this period, the voltage potential of the source and gate of
the external P-FET (M0 in application diagram) should be
almost the same due to the presence of the resistor (R4)
across the source and gate, hence M0 will be off. Please
note that the maximum leakage of DELB in this period is
500nA. To avoid any mis-trigger, the maximum value of R4
should be less than:
Where V
threshold voltage of M0.
After C
turned-on and produces an initial current output of
IDELB_ON1 (~50µA). This current allows the user to control
the turn-on inrush current into the A
capacitors by a suitable choice of C4. This capacitor can
provide extra delay and also filter out any noise coupled into
the gate of M0, avoiding spurious turn-on, however, C4 must
not be so large that it prevents DELB reaching 0.6V by the
end of the start-up sequence on C
ramp on C
for C4. The 0.6V threshold is used by the chip's fault
detection system and if V(DELB) is still above 0.6V at the
end of the power sequencing then a fault time-out ramp will
be initiated on C
When the voltage at DELB falls below ~0.6V, it's current is
increased to IDELB_ON2 (~1.4mA) to firmly pull the DELB
voltage to ground.
R
V
VDD
ON
DLY
DLY
4_max
VDD_delay
OFF
is enabled at the beginning of the sixth ramp.
DLY
capacitor remains at 1.15V until either a fault is
reaches the 4th peak in the start-up sequence. During
soft-starts at the beginning of the third ramp. The
turns on at the start of the fourth peak. At the same
DLY
<
GS(th)_min(M0)
V
------------------------------------------- -
of 220nF, the soft-start time is ~9.6ms.
DLY
GS th
reaches the 4th peak, the internal N-FET is
DLY
(
500nA
Generation Using DELB
will start. A value of 22nF is typically required
)_min(M0)
DLY
rises to 2.4V at which point the chip is
.
VDD
is the minimum value of gate
output.
VDD
18
VDD
.
and A
DLY
VDD_delay
, else a fault time-out
VDD_delayed
DLY
supply
capacitor.
(EQ. 24)
VDD
ISL97650
If the maximum V
voltage being used, then a resistor may be inserted between
the DELB pin and the gate of M0 such that it's potential
divider action with R4 ensures the gate/source stays below
VGS(M0)max. This additional resistor allows much larger
values of C4 to be used, and hence longer A
without affecting the fault protection on DELB.
Component Selection for Start-up Sequencing and
Fault Protection
The C
to stabilize the V
22nF to 1µF and should not be more than five times the
capacitor on CDEL to ensure correct start-up operation.
The CDEL capacitor is typically 220nF and has a usable
range from 47nF minimum to several microfarads - only
limited by the leakage in the capacitor reaching µA levels.
CDEL should be at least 1/5 of the value of C
previous). Note, with 220nF on CDEL, the fault time-out will
be typically 50ms. and the use of a larger/smaller value will
vary this time proportionally (e.g. 1µF will give a fault time-
out period of typically 230ms).
Fault Sequencing
The ISL97650 has advanced overall fault detection systems
including Over Current Protection (OCP) for both boost and
buck converters, Under Voltage Lockout Protection (UVLP)
and Over-Temperature Protection.
Once the peak current flowing through the switching
MOSFET of the boost and buck converters triggers the
current limit threshold, the PWM comparator will disable the
output, cycle by cycle, until the current is back to normal.
The ISL97650 detects each feedback voltage of A
V
feedback is lower than the fault threshold, then a timed fault
ramp will appear on CDEL. If it completes, then V
and A
If V
channels will switch off, and V
to turn them on again.
An internal temperature sensor continuously monitors the
die temperature. In the event that the die temperature
exceeds the thermal trip point of +150°C, the device will shut
down. Operation with die temperatures between +125°C and
+150°C can be tolerated for short periods of time, however,
in order to maximize the operating life of the IC, it is
recommended that the effective continuous operating
junction temperature of the die should not exceed +125°C.
OFF
LOGIC
VDD
REF
and V
feedback is lower than fault threshold, then all
will shut down, but V
capacitor is typically set at 220nF and is required
LOGIC
REF
GS
. If any of the V
voltage of M0 is less than the A
output. The range of C
IN
LOGIC
or Enable needs recycling
ON
, V
will stay on.
OFF
REF
or A
VDD
REF
VDD
is from
VDD
delay,
ON
(see
April 17, 2009
VDD
, V
, V
FN9198.4
OFF
ON
,

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