IDT72T6480L7-5BB IDT, Integrated Device Technology Inc, IDT72T6480L7-5BB Datasheet - Page 11

• Manufacturer Part Number: IDT72T6480L7-5BB
• Description: IC FLOW-CTRL 48BIT 7-5NS 324-BGA
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT72T6480L7-5BB

• Operating Supply Voltage (typ): 2.5V
• Operating Supply Voltage (min): 2.375V
• Operating Supply Voltage (max): 2.625V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 72T6480L7-5BB

DETAILED DESCRIPTIONS
SEQUENTIAL FLOW-CONTROL STRUCTURE
faces: input port, output port, and memory interface. The input and output port
can operate independently of each other with selectable bus widths of x12, x24,
or x48 bits wide. The third interface, or memory interface, is connected directly
to an external memory, which can be used to offload data entering the SFC
device.
WRITING AND READING FROM THE SEQUENTIAL FLOW-CONTROL
DEVICE
(WEN) and write chip select (WCS) low with a free running write clock (WCLK).
Data will be written on the rising edge of every WCLK into the Quad-Port (QP)
cache of the SFC device. The internal state machine of the device will determine
whether to send the data to the DDR SDRAM or send it directly through to the
output bus, depending on when the data is to be accessed. This provides “data
coherency” and minimizes the path that the data has to travel.
TABLE 1 – DDR SDRAM MINIMUM SPECIFICATIONS
TABLE 2 – SUPPORTED MEMORY VENDORS
NOTE
1. These are the minimum specifications that the DDR SDRAM must meet.
NOTES
1. The part numbers listed above include packages that are recommended and validated by IDT.
2. The letter "X" for Samsung memory part numbers denotes the latest die revision for that particular
IDT72T6480 2.5V, SEQUENTIAL FLOW-CONTROL DEVICE
x12, x24, x48 BIT WIDE CONFIGURATION
t
t
t
t
t
t
t
The IDT sequential flow-control (SFC) device is comprised of three inter-
Writing into the SFC device is accomplished by setting the write enable signal
CK
RCD
RP
WR
RCDRD
RCDWR
RFC
Other packages (such as lead free PCB, FBGA, etc.) may also be used but have not been
validated by IDT.
device. Check with Samsung for the latest updated part number.
:
128Mb
256Mb
256Mb
256Mb
256Mb
Density
:
Symbol
CL = 2.5
CL = 3.0
Bus Width
32
16
16
16
32
Clock cycle time
Auto refresh command period
Active to read/write delay
Precharge comman period
Write recovery time
Active to read delay
Active to write delay
DDR SDRAM Minimum Specifications
Parameter
Samsung
Samsung
Micron
Infineon
Samsung
Vendor
K4D263238"X"-GC45
K4H561638"X"-TCLB3
K4H561638"X"-GCLB3
MT46V16M16TG-6T
MT46V16M16TG-75
HYB25D256160BTL-6
HYB25D256160BTL-7
K4D553238"X"-JC50
16-bit DDR
SDRAM
Part#
n/a
n/a
n/a
75
20
20
15
6
11
signal (REN) and read chip select (RCS) low with a free running read clock
(RCLK). Data will be sent to the output bus on the rising edge of every RCLK.
This data will be accessed either from the QP cache or the external DDR
SDRAM.
EXTERNAL MEMORY SELECTION
with standard DDR I specifications. The SFC device can support any external
memory within the following characteristics:
the sequential flow-control device requirements. Table 2 lists the memory
vendors and associated part numbers of DDR SDRAMs that have been
validated by IDT to meet the requirements for the DDR SDRAM interface.
Reading from the SFC device is accomplished by setting the read enable
The DDR SDRAM interface of the SFC device can support DDR SDRAM
•
•
•
Table 1 lists the DDR SDRAM minimum specifications that are required to meet
Bus width: 16-bit or 32-bit wide
Speed: 133MHz or 166MHz
Density: 128Mb or 256Mb
32-bit DDR
SDRAM
n/a
n/a
1.5
63
18
18
6
9
Units
ns
ns
ns
ns
ns
ns
ns
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
FEBRUARY 10, 2009