IDT72T6480L7-5BB IDT, Integrated Device Technology Inc, IDT72T6480L7-5BB Datasheet - Page 49

• Manufacturer Part Number: IDT72T6480L7-5BB
• Description: IC FLOW-CTRL 48BIT 7-5NS 324-BGA
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT72T6480L7-5BB

• Operating Supply Voltage (typ): 2.5V
• Operating Supply Voltage (min): 2.375V
• Operating Supply Voltage (max): 2.625V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 72T6480L7-5BB

DEPTH EXPANSION CONFIGURATION
SFCs in depth expansion to provide additional storage density that’s greater
than 1Gb. In depth expansion mode, two or mode devices are connected
through a common transfer interface, as shown in Figure 34. The transfer clock
can be a separate free-running clock or driven from the same system write or
read clock.
ration will pass from the first SFC to the next until it appears on the second (or
last) SFC in the chain. If no reads are performed, data will begin accumulating
in the second SFC until it is full. Once the second SFC is full it will disable the
REN to the first SFC. At this point data will begin accumulating in the first SFC.
Once both devices are full, the entire configuration is full and the full flag indicator
will go LOW.
the second (or last) SFC in the chain to go LOW (i.e. valid data available to be
IDT72T6480 2.5V, SEQUENTIAL FLOW-CONTROL DEVICE
x12, x24, x48 BIT WIDE CONFIGURATION
The sequential flow-control (SFC) device can be connected with multiple
In depth expansion configuration, the first word written to an empty configu-
For an empty configuration, the amount of time it takes for the empty flag of
Input Ready Flag
Write Enable
Data Inputs
Write Enable
Write Clock
Data Inputs
Write Clock
Full Flag
GND
Transfer Clock
V
Transfer Clock
CC
WCLK
WEN
FF
Dn
WCLK
WEN
IR
Dn
Figure 34. Depth Expansion Configuration in IDT Standard Mode
Figure 35. Depth Expansion Configuration in FWFT Mode
IDEM
FWFT
SFC
V
IDEM
V
#1
GND
CC
FWFT
SFC
CC
#1
RCLK
REN
RCLK
OR
Qn
REN
OR
Qn
49
read out of the device) after a word has been written into the first FIFO is the
sum of the delays for each individual SFC:
in ns. This latency is only noticeable for the first word written to an empty
configuration. There will be no delay evident for subsequent words written into
the chain.
to go from LOW to HIGH after reading one word from the chain is the sum of the
delays for each individual SFC:
Through (FWFT) mode. If IDT Standard mode is selected, the IDEM signal
needs to be HIGH. If FWFT mode is selected, the IDEM signal needs to be LOW.
(N - 1) x (4 x transfer clock) + 3 x RCLK
Where N is the number of SFCs in the chain and RCLK is the RCLK period
In the full configuration, the amount of time it takes for the FF of the first SFC
(N - 1) x (3 x transfer clock) + 2 x WCLK
Depth expansion is available in both IDT Standard mode and First Word Fall
WCLK
WEN
IR
Dn
WCLK
WEN
IR
Dn
FWFT
IDEM
V
SFC
FWFT
IDEM
#2
CC
GND
SFC
#2
RCLK
REN
RCLK
EF
Qn
COMMERCIAL AND INDUSTRIAL
REN
OR
Qn
Data Outputs
Read Clock
Empty Flag
Read Enable
Data Outputs
Output Ready Flag
Read Clock
Read Enable
TEMPERATURE RANGES
6358 drw42
6358 drw43
FEBRUARY 10, 2009