IDT72T6480L7-5BB IDT, Integrated Device Technology Inc, IDT72T6480L7-5BB Datasheet - Page 20

• Manufacturer Part Number: IDT72T6480L7-5BB
• Description: IC FLOW-CTRL 48BIT 7-5NS 324-BGA
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT72T6480L7-5BB

• Operating Supply Voltage (typ): 2.5V
• Operating Supply Voltage (min): 2.375V
• Operating Supply Voltage (max): 2.625V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 72T6480L7-5BB

ERROR DETECTION AND CORRECTION
integrity between the DDR SDRAM interface and the SFC. The EDC corrects
all single bit hard and soft errors that are accessed from the DDR SDRAM.
Multiple bit errors are not detected nor corrected.
correction logic. When the EDC is enabled, the check bit generator will generate
8 syndrome bits on the 8-byte boundary. The 8 syndrome bits are written into
the DDR SDRAM along with the data. The SFC will burst write two cycles for
data, and one cycle for syndrome bits. In order to minimize overhead and
TABLE 8 – MIC[2:0] CONFIGURATIONS
IDT72T6480 2.5V, SEQUENTIAL FLOW-CONTROL DEVICE
x12, x24, x48 BIT WIDE CONFIGURATION
The Error Detection and Correction (EDC) feature is available to ensure data
The EDC logic blocks consist of a check bit generator and error detection
Configuration 1
Configuration 2
Configuration 3
Configuration 4
Configuration 5
Configuration 6
Configuration 7
MIC [2:0] = 000
MIC [2:0] = 001
MIC [2:0] = 111
MIC [2:0] = 100
MIC [2:0] = 000
MIC [2:0] = 100
MIC [2:0] = 111
EDC Off
MIC [2:0] = 010
MIC [2:0] = 011
MIC [2:0] = 101
MIC [2:0] = 110
MIC [2:0] = 010
MIC [2:0] = 110
MIC [2:0] = 101
EDC On
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increase throughput, not all memory in the DDR SDRAM is utilized. Table 5 lists
the total usable memory for all 7 configurations when the EDC is enabled.
to the error detection correction logic block and decoded to determine whether
there are any single bit errors on the data. Single bit errors will be corrected
and data is passed through to the QP cache.
dynamics of the total usable memory in the DDR SDRAM and the SFC operating
speed will vary, listed in Tables 6 and 7. Table 8 shows how to enable the EDC
feature for the 7 configurations
When a read operation is performed, the syndrome bits will be transferred
The EDC is enabled using the MIC[2:0] pins. When the EDC is enabled, the
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
FEBRUARY 10, 2009