IDT72T6480L7-5BB IDT, Integrated Device Technology Inc, IDT72T6480L7-5BB Datasheet - Page 39

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IDT72T6480L7-5BB

Manufacturer Part Number
IDT72T6480L7-5BB
Description
IC FLOW-CTRL 48BIT 7-5NS 324-BGA
Manufacturer
IDT, Integrated Device Technology Inc
Datasheet

Specifications of IDT72T6480L7-5BB

Operating Supply Voltage (typ)
2.5V
Operating Supply Voltage (min)
2.375V
Operating Supply Voltage (max)
2.625V
Operating Temp Range
0C to 70C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
324
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
72T6480L7-5BB

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
IDT72T6480L7-5BB
Manufacturer:
IDT, Integrated Device Technology Inc
Quantity:
10 000
Part Number:
IDT72T6480L7-5BBG
Manufacturer:
IDT, Integrated Device Technology Inc
Quantity:
10 000
IDT72T6480 2.5V, SEQUENTIAL FLOW-CONTROL DEVICE
x12, x24, x48 BIT WIDE CONFIGURATION
D[11:0]
Q[47:0]
D[23:0]
Q[47:0]
Symbol
t
t
t
t
t
t
t
DH
A
DS
ENS
ENH
REFs
SKEW1
WCLK
WCLK
RCLK
RCLK
WEN
WEN
REN
REN
NOTES:
1. t
2. Settings: OE = LOW, RCS = LOW, WCS = LOW, BM[3:0] = 1001, FWFT = LOW, ASYR = HIGH, and ASYW = HIGH.
NOTES:
1. t
2. Settings: OE = LOW, RCS = LOW, WCS = LOW, BM[3:0] = 1101, FWFT = LOW, ASYR = HIGH, and ASYW = HIGH.
EF
EF
(plus t
(plus t
SKEW1
SKEW1
Data Setup Time
Data Hold Time
Enable Setup Time
Enable Hold Time
Data Access Time
Read Clock to Synchronous EF/OR
Skew time between RCLK and WCLK for EF/OR and FF/IR in SDR
REFs
REFs
is the minimum time between a rising WCLK edge and a rising RCLK edge to guarantee that EF will go HIGH after one RCLK cycle
is the minimum time between a rising WCLK edge and a rising RCLK edge to guarantee that EF will go HIGH after one RCLK cycle
). If t
). If t
SKEW1
SKEW1
Word 0 Q[11:0]
Figure 19. Bus-Matching Configuration - x24 In to x48 Out - IDT Standard Mode
Figure 20. Bus-Matching Configuration - x12 In to x48 Out - IDT Standard Mode
t
t
DS
ENS
is not met, then EF de-assertion may be delayed one extra RCLK cycle.
Parameter
is not met, then EF de-assertion may be delayed one extra RCLK cycle.
Word 0 Q[23:0]
t
DS
t
t
ENS
DH
Word 0 Q[23:12]
t
DH
Word 0 Q[23:0]
t
DS
Previous Word in Register
Previous Word in Register
t
Word 0 Q[35:24]
t
SKEW1
ENH
t
DH
1
39
Word 0 Q[47:36]
(x24 or x12 I/O only) (x48 I/O width only)
Min.
0.5
0.5
t
2
2
1
4
t
t
REFS
SKEW1
ENH
2
7-5ns
1
Max.
t
ENS
4
4
t
t
REFS
ENH
Min.
t
2.5
0.5
2.5
0.5
A
1
5
7-5ns
t
REFS
2
Max.
COMMERCIAL AND INDUSTRIAL
5
5
t
ENS
Word 0
TEMPERATURE RANGES
Min.
t
3.5
0.5
3.5
0.5
t
REFS
ENH
1
7
3
t
A
10ns
FEBRUARY 10, 2009
Max.
6.5
6.5
6358 drw27
Word 0
6358 drw28
Unit
ns
ns
ns
ns
ns
ns
ns

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