IDT72T6480L7-5BB IDT, Integrated Device Technology Inc, IDT72T6480L7-5BB Datasheet - Page 38

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IDT72T6480L7-5BB

Manufacturer Part Number
IDT72T6480L7-5BB
Description
IC FLOW-CTRL 48BIT 7-5NS 324-BGA
Manufacturer
IDT, Integrated Device Technology Inc
Datasheet

Specifications of IDT72T6480L7-5BB

Operating Supply Voltage (typ)
2.5V
Operating Supply Voltage (min)
2.375V
Operating Supply Voltage (max)
2.625V
Operating Temp Range
0C to 70C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
324
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
72T6480L7-5BB

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
IDT72T6480L7-5BB
Manufacturer:
IDT, Integrated Device Technology Inc
Quantity:
10 000
Part Number:
IDT72T6480L7-5BBG
Manufacturer:
IDT, Integrated Device Technology Inc
Quantity:
10 000
IDT72T6480 2.5V, SEQUENTIAL FLOW-CONTROL DEVICE
x12, x24, x48 BIT WIDE CONFIGURATION
Symbol
t
t
t
t
t
t
t
DS
DH
ENS
ENH
A
REFs
SKEW1
D[47:0]
Q[11:0]
D[47:0]
Q[23:0]
WCLK
RCLK
WCLK
NOTES:
1. t
2. Settings: OE = LOW, RCS = LOW, WCS = LOW, BM[3:0] = 1011, FWFT = LOW, ASYR = HIGH, and ASYW = HIGH.
NOTES:
1. t
2. Settings: OE = LOW, RCS = LOW, WCS = LOW, BM[3:0] = 1111, FWFT = LOW, ASYR = HIGH, and ASYW = HIGH.
RCLK
WEN
REN
WEN
REN
cycle (plus t
(plus t
EF
SKEW1
SKEW1
EF
Data Setup Time
Data Hold Time
Enable Setup Time
Enable Hold Time
Data Access Time
Read Clock to Synchronous EF/OR
Skew time between RCLK and WCLK for EF/OR and FF/IR in SDR
REFs
is the minimum time between a rising WCLK edge and a rising RCLK edge to guarantee that EF will go HIGH after one RCLK
is the minimum time between a rising WCLK edge and a rising RCLK edge to guarantee that EF will go HIGH after one RCLK cycle
). If t
REFs
SKEW1
). If t
Figure 18. Bus-Matching Configuration - x48 In to x12 Out - IDT Standard Mode
Figure 17. Bus-Matching Configuration - x48 In to x24 Out - IDT Standard Mode
SKEW1
is not met, then EF de-assertion may be delayed one extra RCLK cycle.
Parameter
t
DS
t
ENS
Word 0
Previous Word in Register D[47:24]
Previous Word in Register D[47:36]
t
is not met, then EF de-assertion may be delayed one extra RCLK cycle.
DS
t
ENS
t
Word 0
SKEW1
t
t
ENH
DH
t
SKEW1
t
t
ENH
DH
1
1
t
REFS
2
t
REFs
2
t
ENS
38
t
A
t
ENS
(x24 or x12 I/O only) (x48 I/O width only)
Word 0 D[11:0]
Min.
0.5
0.5
2
2
1
4
t
A
7-5ns
Word 0 D[23:0]
t
A
Max.
4
4
Word 0 D[23:12]
t
t
ENH
REFs
t
Min.
A
2.5
0.5
2.5
0.5
1
5
t
7-5ns
A
Word 0 D[35:24]
Max.
COMMERCIAL AND INDUSTRIAL
5
5
Word 0 D[47:24]
t
REFS
t
TEMPERATURE RANGES
A
Min.
3.5
0.5
3.5
0.5
1
7
10ns
FEBRUARY 10, 2009
Word 0 D[47:36]
Max.
6.5
6.5
6358 drw25
6358 drw26
Unit
ns
ns
ns
ns
ns
ns
ns

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