IDT72T6480L7-5BB IDT, Integrated Device Technology Inc, IDT72T6480L7-5BB Datasheet - Page 40

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IDT72T6480L7-5BB

Manufacturer Part Number
IDT72T6480L7-5BB
Description
IC FLOW-CTRL 48BIT 7-5NS 324-BGA
Manufacturer
IDT, Integrated Device Technology Inc
Datasheet

Specifications of IDT72T6480L7-5BB

Operating Supply Voltage (typ)
2.5V
Operating Supply Voltage (min)
2.375V
Operating Supply Voltage (max)
2.625V
Operating Temp Range
0C to 70C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
324
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
72T6480L7-5BB

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
IDT72T6480L7-5BB
Manufacturer:
IDT, Integrated Device Technology Inc
Quantity:
10 000
Part Number:
IDT72T6480L7-5BBG
Manufacturer:
IDT, Integrated Device Technology Inc
Quantity:
10 000
IDT72T6480 2.5V, SEQUENTIAL FLOW-CONTROL DEVICE
x12, x24, x48 BIT WIDE CONFIGURATION
D[47:0]
Q[47:0]
D[47:0]
Q[47:0]
WCLK
Symbol
t
t
t
t
t
t
t
WCLK
DS
DH
ENH
A
RCLK
PAFs
PAEs
SKEW2
RCLK
WEN
WEN
REN
REN
NOTES:
1. t
2. n = PAE offset, see Table 10 for information on setting PAE offset values.
3. Settings: OE = LOW, RCS = LOW, BM[3:0] = 1000, ASYR = HIGH, and ASYW = HIGH.
PAE
PAF
NOTES:
1. t
2. m = PAF offset, D = density of SFC, see Table 11 for information on setting PAF offset values.
3. Settings: OE = LOW, RCS = LOW, BM[3:0] = 1000, ASYR = HIGH, and ASYW = HIGH.
cycle (plus t
SKEW2
cycle (plus t
SKEW2
Data Setup Time
Data Hold Time
Enable Hold Time
Data Access Time
WCLK to Synchronous PAF
RCLK to Synchronous PAE
Skew time between RCLK and WCLK for PAE/PAF
Word D - (m + 1)
is the minimum time between a rising WCLK edge and a rising RCLK edge to guarantee that PAE will go HIGH after one RCLK
is the minimum time between a rising WCLK edge and a rising RCLK edge to guarantee that PAF will go HIGH after one RCLK
PAEs
PAFs
t
Word n + 1
n words or less in Memory
n + 1 words or less in Memory
). If t
DS
). If t
SKEW2
t
SKEW2
SKEW2
t
t
Parameter
ENH
DH
Word D - m
Figure 22. Synchronous PAF
t
Figure 21. Synchronous PAE
DS
is not met, then PAE de-assertion may be delayed one extra RCLK cycle.
is not met, then PAF de-assertion may be delayed one extra RCLK cycle.
1
t
t
DH
DH
(2)
D - (m + 1) words or less in Memory
Previous Word in Register
(2)
Previous Word in Register
t
PAEs
2
1
PAF
PAF
PAF Flag - IDT Standard Mode and FWFT Mode
PAF
PAE
PAE
PAE Flag - IDT Standard Mode and FWFT Mode
PAE
40
t
2
PAFs
t
ENS
n + 1 words or more in Memory
n + 2 words or more in Memory
(x24 or x12 I/O only) (x48 I/O width only)
Min.
0.5
0.5
2
1
5
t
ENH
7-5ns
t
A
t
ENS
D - m words or more in Memory
Max.
4
4
4
t
t
ENH
SKEW2
t
A
1
(2)
Min.
(2)
2.5
0.5
0.5
1
7
7-5ns
1
Word 0
Max.
COMMERCIAL AND INDUSTRIAL
5
5
5
t
PAEs
2
Word 0
TEMPERATURE RANGES
Min.
t
2
3.5
0.5
0.5
PAFs
10
6358 drw29
1
10ns
6358 drw30
FEBRUARY 10, 2009
Max.
6.5
6.5
6.5
Unit
ns
ns
ns
ns
ns
ns
ns

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