KS8999 Micrel Inc, KS8999 Datasheet
KS8999
Specifications of KS8999
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KS8999 Summary of contents
Page 1
... January 2005 KS8999 Integrated 9-Port 10/100 Switch with PHY and Frame Buffer Rev. 1.14 KS8999 is designed to reside in an unmanaged design not requiring processor intervention. This is achieved through I/O strapping or EEPROM programming at system reset time.On the media side, the KS8999 supports 10BaseT, 100BaseTX and 100BaseFX as specified by the IEEE 802 ...
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... Supports lead free products: – Commercial temperature range +70 C (KSZ8999) – Industrial temperature range: – +85 C (KSZ8999I) • Available in 208-pin PQFP package KS8999 Ordering Information Part Number Temperature Range KS8999 +70 C KS8999I – +85 C KSZ8999 +70 C KSZ8999I – + Micrel Package ...
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... Correct default to floating for pin 174 Change pin 87 TEST[3] to AUTOMDIX for enable/disable of auto MDI-MDIX function 1.10 2/27/03 Add KS8999I industrial temperature Update non-periodic blinking in Mode 1 of LED[1:9][0] Add MRXD[0] description 1.11 5/12/03 Changed Vcc from 2.00 to 2.10 (typical) Added FEF disable to T[4] pin #173 1 ...
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... Half-Duplex Back Pressure .......................................................................................................................... 23 Broadcast Storm Protection ................................................................................................................................. 23 MII Interface Operation .............................................................................................................................................. 24 SNI Interface (7-wire) Operation ............................................................................................................................... 26 Prorammable Features .............................................................................................................................................. 26 Priority Schemes .................................................................................................................................................. 26 Per Port Method ................................................................................................................................................... 26 802.1p Method ..................................................................................................................................................... 26 IPv4 DSCP Method .............................................................................................................................................. 26 Other Priority Considerations ............................................................................................................................... 26 VLAN Operation ......................................................................................................................................................... 27 Station MAC Address ................................................................................................................................................ 27 EEPROM Operation ................................................................................................................................................... 28 Optional CPU Interface ............................................................................................................................................. 28 KS8999 4 Micrel January 2005 ...
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... Port 8 VLAN Tag Insertion Value Registers ................................................................................................. 38 Port 9 VLAN Tag Insertion Value Registers ................................................................................................. 38 Diff Serve Code Point Registers .................................................................................................................. 38 Station MAC Address Registers .................................................................................................................. 38 Absolute Maximum Ratings ..................................................................................................................................... 39 Operating Ratings ..................................................................................................................................................... 39 Electrical Characteristics (KS8999) ......................................................................................................................... 39 Electrical Characteristics (KS8999I) ........................................................................................................................ 41 Timing Diagrams ....................................................................................................................................................... 42 Reference Circuit ....................................................................................................................................................... 47 4B/5B Coding ........................................................................................................................................................... 49 MLT Coding ........................................................................................................................................................... 50 MAC Frame ...
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... KS8999 System Level Applications The KS8999 can be configured to fit either in an eight port 10/ 100 application nine port 10/100 network interface with an extra MII/7-wire port. This MII/7-wire port can be connected to an external processor and used for routing KS8999 8-Port Switch with PHY ...
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... Set physical transmit output current Analog ground Pwr 2.0V for equalizer Ground for equalizer I 5 Physical receive signal + (differential Physical receive signal - (differential) Ground for transmit circuitry O 5 Physical transmit signal + (differential Physical transmit signal - (differential) 7 Micrel KS8999 ...
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... Ipu = input w/ internal pull-up Ipd = input w/ internal pull-down Opu = output w/ internal pull-up Opd = output w/ internal pull-down Ipd/O = input w/ internal pull-down during reset, output pin otherwise Ipu/O = input w/ internal pull-up during reset, output pin otherwise KS8999 (Note 1) Port Pin Function Analog ground Pwr 2 ...
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... Ground for digital circuitry Ipd 9 MII transmit enable Ipd 9 MII transmit bit 3 Ipd 9 MII transmit bit 2 Ipd 9 MII transmit bit 1 Ipd 9 MII transmit bit 0 Ipd 9 MII transmit error 9 MII transmit clock 9 MII collision detected 9 MII carrier sense 9 Micrel KS8999 ...
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... Ipd = input w/ internal pull-down Opu = output w/ internal pull-up Opd = output w/ internal pull-down Ipd/O = input w/ internal pull-down during reset, output pin otherwise Ipu/O = input w/ internal pull-up during reset, output pin otherwise KS8999 (Note 1) Port Pin Function Pwr 2.0V, 2.5V or 3.3V for I/O circuitry ...
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... Factory test pin – tie low for normal operation Ipd Reserve 6KB buffer for priority frames Ipu Configures programming interface for EEPROM or processor I Factory test pin – float for normal operation F/D = normal operation (default disable FEF I Reserved – floating for normal operation 11 Micrel KS8999 ...
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... Ipu = input w/ internal pull-up Ipd = input w/ internal pull-down Opu = output w/ internal pull-up Opd = output w/ internal pull-down Ipd/O = input w/ internal pull-down during reset, output pin otherwise Ipu/O = input w/ internal pull-up during reset, output pin otherwise KS8999 (Note 1) Port Pin Function I Reserved - floating for normal operation ...
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... Collision detection SNI receive clock SNI transmit clock Output (after reset) Mode 0: Speed (on = 100/off = 10) Mode 1: 10/100 + link + activity 10Mb link activity = slow blink (non-periodic blinking) 100Mb link activity = fast blink (non-periodic blinking) Mode 2: Collision (on = collision/off = no collision) Mode 3: Speed (on = 100/off = 10) 13 Micrel KS8999 ...
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... LED[1][1] Note 1. All unmanaged programming takes place at reset time only. For unmanaged programming Float Pull-down Pull-up. “Reference Circuits” See section. KS8999 (Note 1) Description Output (after reset) Mode 0: Full Duplex (on = full/off = half) Mode 1: Full Duplex (on = full/off = half) Mode 2: Full Duplex (on = full/off = half) ...
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... D = Full-duplex, F/U = Half-duplex (default) Programs port duplex (full/ half) on port 6. This is only effective if auto-negotiation is disabled or if this end has auto-negotiation enabled and the far end has auto- negotiation disabled Full-duplex, F/U = Half-duplex (default) 15 Micrel KS8999 ...
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... All unmanaged programming takes place at reset time only. For unmanaged programming Float Pull-down Pull-up. “Reference Circuits” See section. KS8999 (Note 1) Description Programs port duplex (full / half) on port 7. This is only effective if auto-negotiation is disabled or if this end has auto-negotiation enabled and the far end has auto- negotiation disabled ...
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... Factory test input – tie low for normal operation Factory test input – tie low for normal operation 2.0V for equalizer Ground for equalizer 2.0V for transmit circuitry Ground for transmit circuitry 2.0V for clock recovery circuitry Ground for clock recovery 2.0V for phase locked loop circuitry 17 Micrel KS8999 ...
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... KS8999 Group I/O Names Active Status GND_PLLTX GND-ISO VDD VDD-IO GND KS8999 Description Ground for phase locked loop circuitry Analog ground 2.0V for core digital circuitry 2.0V, 2.5V or 3.3V for I/O circuitry Ground for digital circuitry 18 Micrel January 2005 ...
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... SDA EN1P T[3] T[2] T[1] AUTOMDIX TEST[2] TEST[1] MUX[2] MUX[1] RLPBK CTOUT2 BTOUT2 VDD_RCV VDD_RCV GND_RCV GND_RCV VDD_RCV VDD_RCV GND_RCV GND_RCV FXSD[8] FXSD[7] FXSD[6] FXSD[5] VDD_RX GND_RX RXM[8] RXP[8] GND_TX TXM[8] TXP[8] VDD_TX VDD_TX TXM[7] TXP[7] GND_TX RXM[7] RXP[7] 53 GND_ISO KS8999 ...
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... RXP or RXM input from falsely triggering the decoder. When the input exceeds the squelch limit, the PLL locks onto the incoming signal and the KS8999 decodes a data frame. The receiver clock is maintained active during idle periods in between data reception. KS8999 ...
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... Power Save Mode The KS8999 will turn off everything except for the Energy Detect and PLL circuits when the cable is not installed on an individual port basis. In other words, the KS8999 will shutdown most of the internal circuits to save power if there is no link. ...
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... If the DA look-up results is a “match”, the KS8999 will use the destination port information to determine where the packet goes. • If the DA look-up result is a “miss”, the KS8999 will forward the packet to all other ports except the port that received the packet. ...
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... IEEE standard 802.3x. Once the resource is freed up, the KS8999 will send out the other flow control frame (XON) with zero pause time to turn off the flow control (turn on transmission to the port). A hysteresis feature is provided to prevent flow control mechanism from being activated and deactivated too many times ...
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... KS8999 MII Interface Operation The MII (Media Independent Interface) operates in either a MAC or PHY mode. In the MAC mode, the KS8999 MII acts like a MAC and in the PHY mode, it acts like a PHY device. This interface is specified by the IEEE 802.3 committee and provides a common interface between physical layer and MAC layer devices. There are two distinct groups, one being for transmission and the other for receiving ...
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... KS8999 Note that the signal MRXER is not provided on the MII interface for the KS8999 for PHY mode operation and MTXER is not represented for MAC mode. Normally this would indicate a receive / transmit error coming from the physical layer /MAC device, but is not appropriate for this configuration. If the connecting device has a MRXER pin, this should be tied low on the other device for reverse has a MTXER pin in the forward mode it should also be tied low on the other device ...
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... Priority Schemes The KS8999 can determine priority through three different means at the ingress point. The first method is a simple per port method, the second is via the 802.1p frame tag and the third is by viewing the DSCP (TOS) field in the IPv4 header. Of course for the priority to be effective, the high and low priority queues must be enabled on the destination port or egress point ...
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... VLAN Mask Registers: Allows configuration of individual VLAN grouping. VLAN Tag Insertion Values: Specifies the VLAN tag to be inserted if enabled (see above) Table 4. VLAN Control Description Station MAC Address: Used as source address for MAC control frames as used in full duplex flow control mechanisms. Table 5. Misc. Control 27 Micrel KS8999 ...
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... Instead of using an EEPROM to program the KS8999, one can use an external processor. To utilize this feature, the CFGMODE pin (only available on the 208 pin package) needs to pulled low. This makes the KS8999 serial and clock interface into a slave rather than a master. In this mode, clock and data are sourced from the processor. ...
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... Enable 0 = Disable Port based priority classification for port High priority 0 = Low priority Insert VLAN tags for port 1 if non-existent 1 = Enable 0 = Disable Strip VLAN tags for port 1 if existent 1 = Enable 0 = Disable 29 Micrel Default (chip) Value 0x55 0x99 0000 KS8999 ...
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... Port 4 Control Register 7 7 KS8999 Description Enable high and low output priority queues for port Enable 0 = Disable Reserved – set to zero TOS priority classification enable for port Enable 0 = Disable 802.1p priority classification enable for port Enable 0 = Disable Port based priority classification for port 2 ...
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... Port based priority classification for port High priority 0 = Low priority Insert VLAN tags for port 6 if non-existent 1 = Enable 0 = Disable Strip VLAN tags for port 6 if existent 1 = Enable 0 = Disable Enable high and low output priority queues for port Enable 0 = Disable 31 Micrel Default (chip) Value KS8999 ...
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... Port 9 Control Register 12 7 KS8999 Description Reserved – set to zero TOS priority classification enable for port Enable 0 = Disable 802.1p priority classification enable for port Enable 0 = Disable Port based priority classification for port High priority 0 = Low priority Insert VLAN tags for port 7 if non-existent ...
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... Port 6 in the same VLAN as port Port 6 not in the same VLAN as port 2 Port 5 inclusion 1 = Port 5 in the same VLAN as port Port 5 not in the same VLAN as port 2 Port 4 inclusion 1 = Port 4 in the same VLAN as port Port 4 not in the same VLAN as port 2 33 Micrel Default (chip) Value KS8999 ...
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... KS8999 Description Port 3 inclusion 1 = Port 3 in the same VLAN as port Port 3 not in the same VLAN as port 2 Port 1 inclusion 1 = Port 1 in the same VLAN as port Port 1 not in the same VLAN as port 2 Port 9 inclusion 1 = Port 9 in the same VLAN as port Port 9 not in the same VLAN as port 3 ...
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... Port 3 in the same VLAN as port Port 3 not in the same VLAN as port 6 Port 2 inclusion 1 = Port 2 in the same VLAN as port Port 2 not in the same VLAN as port 6 Port 1 inclusion 1 = Port 1 in the same VLAN as port Port 1 not in the same VLAN as port 6 35 Micrel Default (chip) Value KS8999 ...
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... KS8999 Description Port 9 inclusion 1 = Port 9 in the same VLAN as port Port 9 not in the same VLAN as port 7 Port 8 inclusion 1 = Port 8 in the same VLAN as port Port 8 not in the same VLAN as port 7 Port 6 inclusion 1 = Port 6 in the same VLAN as port Port 6 not in the same VLAN as port 7 ...
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... User priority [2:0] CFI VID [11:8] VID [7:0] User priority [2:0] CFI VID [11:8] VID [7:0] User priority [2:0] CFI VID [11:8] VID [7:0] 37 Micrel Default (chip) Value 000 0 0x0 0x00 000 0 0x0 0x00 000 0 0x0 0x00 000 0 0x0 0x00 KS8999 ...
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... Note: The MAC address is reset to the value in the above table, but can set to any value via the EEPROM interface. This MAC address is used as the source address in MAC control frames that execute flow control between link peers. KS8999 Description User priority [2:0] ...
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... DD_PLLTX (V ) .................................................... –0.5V to +3.8V DDIO Input Voltage ............................................... –0.5V to +4.0V Output Voltage ............................................ –0.5V to +4.0V Lead Temperature (soldering, 10 sec.) ..................... 270 C Storage Temperature (T ) ....................... – +150 C S Electrical Characteristics (KS8999 2.0V to 2.3V +70 ; unless noted Symbol Parameter V Supply Voltage DD Supply Current (including TX output driver current) 100BaseTX Operation— ...
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... Reference Voltage of ISET SET Output Jitters 10BaseTX Receive V Squelch Threshold SQ 10BaseT Transmit (measured differentially after 1:1 transformer) V Peak Differential Output Voltage P Jitters Added Rise/Fall Times KS8999 Condition Peak-to-peak 5MHz square wave 50 from each output from each output Micrel Min Typ Max Units 0 ...
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... Parameter t Clock Cycle CYC t Output Valid OV January 2005 Figure 7. EEPROM Input Timing Table 5. EEPROM Input Timing Parameters Figure 8. EEPROM Output Timing Table 6. EEPROM Output Timing Parameters 41 Micrel Min Typ Max Units 16384 Min Typ Max Units 16384 ns 4096 4112 4128 ns KS8999 ...
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... Set-Up Time S t Hold Time H Symbol Parameter t Clock Cycle CYC t Output Valid OV KS8999 Figure 9. SNI (7-wire) Input Timing Table 7. SNI (7-wire) Input Parameters Figure 10. SNI (7-wire) Output Timing Table 8. SNI (7-wire) Output Timing Parameters 42 Micrel Min Typ Max Units 100 ns 10 ...
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... KS8999 Figure 11. KS8999 PHY Mode—Data Sent from External MAC Controller to KS8999 Symbol Parameter t Clock Cycle (100BaseT) CYC t Clock Cycle (10BaseT) CYC t Set-Up Time S t Hold Time H Table 9. MII Timing in KS8999 PHY and MAC Mode Timing Parameters January 2005 Figure 12. KS8999 PHY Mode Receive Timing ...
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... KS8999 Figure 13. KS8999 PHY Mode—Data Sent from KS8999 PHY Mode to External MAC Controller Symbol Parameter t Clock Cycle (100BaseT) CYC t Clock Cycle (10BaseT) CYC t Output Valid OV Table 10. KS8999 PHY Mode Transmit Timing Parameters KS8999 Figure 14. KS8999 PHY Mode Transmit Timing 44 Micrel ...
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... KS8999 Figure 15. KS8999 MAC Mode—Data Sent from External PHY Device to KS8999 Symbol Parameter t Clock Cycle (100BaseT) CYC t Clock Cycle (10BaseT) CYC t Output Valid S t Output Valid H Table 11. KS8999 PHY Mode Transmit Timing Parameters January 2005 Figure 16. KS8999 MAC Mode Receive Timing ...
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... KS8999 Figure 17. KS8999 MAC Mode Timing—Data Sent from KS8999 MAC mode to External PHY Device Symbol Parameter t Clock Cycle (100BaseT) CYC t Clock Cycle (10BaseT) CYC t Output Valid OV Table 12. KS8999 MAC Mode Transmit Timing Parameters KS8999 Figure 18. KS8999 MAC Mode Transmit Timing ...
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... Reset Reference Circuit Micrel recommendeds the following discrete reset circuit as shown in Figure 20 when powering up the KS8999 device. For the application where the reset circuit signal comes from another device (e.g., CPU, FPGA, etc), we recommend the reset circuit as shown in Figure 21 ...
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... Figure 21. Recommended Circuit for Interfacing with CPU/FPGA Reset At power-on-reset and D1 provide the necessary ramp rise time to reset the KS8999 device. The reset out from CPU/ FPGA provides warm reset after power up also recommended to power up the VDD core voltage earlier than VDDIO voltage ...
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... Data value E Data value F Idle Start delimiter part 1 Start delimiter part 2 End delimiter part 1 End delimiter part 2 Transmit error Invalid code Invalid code Invalid code Invalid code Invalid code Invalid code Invalid code Invalid code Invalid code Invalid code Micrel KS8999 ...
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... Preamble/SFD Length 2 Protocol/Data 46 to 1500 Frame CRC 4 ESD 1 Idle Variable KS8999 1010 0011 1000 1110 1001 0100 UUUU UUUU UUUU UUUU 10110101011001011100100110101001101001111111111111 Figure 20. MLT3 coding Description Preamble and Start of Frame Delimiter 48-bit Destination MAC Address 48-bit Source MAC Address Frame Length ...
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... Yes 4 Transpower Yes 4 Delta Table 15. Qualified Magnetics Vendor Lists 51 Test Condition 100mV, 100 KHz, 8mA 1MHz (min.) 0MHz to 65MHz Test Condition MHz ppm ps(pk-pk) Auto Part MDIX H1102 Yes S558-5999-U7 Yes PT163020 Yes HB726 Yes LF8505 Yes Micrel Number of Port KS8999 ...
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... A Purchaser’s use or sale of Micrel Products for use in life support appliances, devices or systems is at Purchaser’s own risk and Purchaser agrees to fully indemnify KS8999 208-Pin PQFP (PQ) ...