KS8999 Micrel Inc, KS8999 Datasheet - Page 20

• Manufacturer Part Number: KS8999
• Description: IC SWITCH 10/100 9PORT 208PQFP
• Manufacturer: Micrel Inc

Specifications of KS8999

• Applications: *
• Mounting Type: Surface Mount
• Package / Case: 208-MQFP, 208-PQFP
• Fiber Support: Yes
• Integrated Led Drivers: Yes
• Phy/transceiver Interface: MII/SNI
• Power Supply Type: Analog/Digital
• Package Type: PQFP
• Data Rate (typ): 10/100Mbps
• Vlan Support: Yes
• Operating Temperature (max): 70C
• Operating Temperature (min): 0C
• Mounting: Surface Mount
• Jtag Support: No
• Operating Temperature Classification: Commercial
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• For Use With: 576-1023 - BOARD EVAL EXPERIMENT FOR KS8999
• Lead Free Status / RoHS Status: Not Compliant, Contains lead / RoHS non-compliant

KS8999
Micrel
Functional Overview: Physical Layer Transceiver
100BaseTX Transmit
The 100BaseTX transmit function performs parallel to serial conversion, 4B/5B coding, scrambling, NRZ to NRZI conver-
sion, MLT3 encoding and transmission. The circuit starts with a parallel to serial conversion, which converts the data from
the MAC into a 125MHz serial bit stream. The data and control stream is then converted into 4B/5B coding followed by a
scrambler. The serialized data is further converted from NRZ to NRZI format, then transmitted in MLT3 current output.
The output current is set by an external 1% 3.01k resistor for the 1:1 transformer ratio. It has a typical rise/fall time of 4
ns and complies to the ANSI TP-PMD standard regarding amplitude balance, overshoot and timing jitters. The wave-
shaped 10BaseT output is also incorporated into the 100BaseTX transmitter.
100BaseTX Receive
The 100BaseTX receiver function performs adaptive equalization, DC restoration, MLT3 to NRZI conversion, data and
clock recovery, NRZI to NRZ conversion, de-scrambling, 4B/5B decoding and serial to parallel conversion. The receiving
side starts with the equalization filter to compensate inter-symbol interference (ISI) over the twisted pair cable. Since the
amplitude loss and phase distortion is a function of the length of the cable, the equalizer has to adjust its characteristics to
optimize the performance. This is an ongoing process and can self adjust to the environmental changes such as tempera-
ture variations. The equalized signal then goes through a DC restoration and data conversion block. The DC restoration
circuit is used to compensate for the effect of base line wander and improve the dynamic range. The differential data
conversion circuit converts the MLT3 format back to NRZI. The slicing threshold is also adaptive. The clock recovery
circuit extracts the 125MHz clock from the edges of the NRZI signal. This recovered clock is then used to convert the
NRZI signal into the NRZ format. The signal is then sent through the de-scrambler followed by the 4B/5B decoder. Finally,
the NRZ serial data is provided as the input data to the MAC.
PLL Clock Synthesizer
The KS8999 generates 125MHz, 62.5MHz, 25MHz and 10MHz clocks for system timing. Internal clocks are generated
from an external 25MHz crystal.
Scrambler/De-scrambler (100BaseTX only)
The purpose of the scrambler is to spread the power spectrum of the signal in order to reduce EMI and baseline wander.
The data is scrambled by the use of an 11-bit wide linear feedback shift register (LFSR). This can generate a 2047-bit
non-repetitive sequence. The receiver will then de-scramble the incoming data stream with the same sequence at the
transmitter.
100BaseFX Operation
100BaseFX operation is very similar to 100BaseTX operation with the differences being that the scrambler/de-scrambler
and MLT3 encoder/decoder are bypassed on transmission and reception. In this mode the auto-negotiation feature is
bypassed since there is no standard that supports fiber auto-negotiation.
100BaseFX Signal Detection
The physical port runs in 100BaseFX mode if FXSDx >0.6V. FXSDx is considered ‘low’ when 0.6V<FXSDx<1.25V and
considered ‘high’ when FXSDx>1.25V. If FXSDx goes into ‘low’ state, the link is considered lost and the link active LED
will go off. For FXSDx in the high state, the link is considered active. When FXSDx is below .6V then 100BaseFX mode is
disabled. (see application note for detailed information).
100BaseFX Far End Fault
Far end fault occurs when the signal detection is logically false from the receive fiber module which occurs when FXSDx is
below 1.2V and above 0.6V. When this occurs, the transmission side signals the other end of the link by sending 84 1’s followed
by a zero in the idle period between frames.
10BaseT Transmit
The output 10BaseT driver is incorporated into the 100BaseT driver to allow transmission with the same magnetics. They are
internally wave-shaped and pre-emphasized into outputs with a typical 2.3V amplitude.
10BaseT Receive
On the receive side, input buffer and level detecting squelch circuits are employed. A differential input receiver circuit and a
PLL perform the decoding function. The Manchester-encoded data stream is separated into clock signal and NRZ data. A
squelch circuit rejects signals with levels less than 400mV or with short pulse widths in order to prevent noises at the RXP or
RXM input from falsely triggering the decoder. When the input exceeds the squelch limit, the PLL locks onto the incoming signal
and the KS8999 decodes a data frame. The receiver clock is maintained active during idle periods in between data reception.
KS8999
20
January 2005