ADC08D1020DEV/NOPB National Semiconductor, ADC08D1020DEV/NOPB Datasheet - Page 26

• Manufacturer Part Number: ADC08D1020DEV/NOPB
• Description: BOARD DEV FOR ADC08D1020
• Manufacturer: National Semiconductor
• Series: PowerWise®r

Specifications of ADC08D1020DEV/NOPB

• Number Of Adc's: 2
• Number Of Bits: 8
• Sampling Rate (per Second): 1G
• Data Interface: Serial
• Inputs Per Adc: 1 Differential
• Input Range: 870 mVpp
• Power (typ) @ Conditions: 1.6W @ 1GSPS
• Voltage Supply Source: Single Supply
• Operating Temperature: -40°C ~ 85°C
• Utilized Ic / Part: ADC08D1020
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: ADC08D1020DEV

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1.0 Functional Description
The ADC08D1020 is a versatile A/D Converter with an inno-
vative architecture permitting very high speed operation. The
controls available ease the application of the device to circuit
solutions. Optimum performance requires adherence to the
provisions discussed here and in the Applications Information
Section.
While it is generally poor practice to allow an active pin to float,
pins 4, 14 and 127 of the ADC08D1020 are designed to be
left floating without jeopardy. In all discussions throughout this
data sheet, whenever a function is called by allowing a control
pin to float, connecting that pin to a potential of one half the
V
float.
1.1 OVERVIEW
The ADC08D1020 uses a calibrated folding and interpolating
architecture that achieves 7.4 effective bits. The use of folding
amplifiers greatly reduces the number of comparators and
power consumption. Interpolation reduces the number of
front-end amplifiers required, minimizing the load on the input
signal and further reducing power requirements. In addition
to other things, on-chip calibration reduces the INL bow often
seen with folding architectures. The result is an extremely
fast, high performance, low power converter.
The analog input signal that is within the converter's input
voltage range is digitized to eight bits at speeds of 200 MSPS
to 1.3 GSPS, typical. Differential input voltages below nega-
tive full-scale will cause the output word to consist of all
zeroes. Differential input voltages above positive full-scale
will cause the output word to consist of all ones. Either of
these conditions at either the "I" or "Q" input will cause the OR
(Out of Range) output to be activated. This single OR output
indicates when the output code from one or both of the chan-
nels is below negative full scale or above positive full scale.
Each converter has a selectable output demultiplexer which
feeds two LVDS buses. If the 1:2 demultiplexed mode is se-
lected, the output data rate is reduced to half the input sample
rate on each bus. When non-demultiplexed mode is selected,
that output data rate on channels DI and DQ are at the same
rate as the input sample clock.
The output levels may be selected to be normal or reduced.
Using reduced levels saves power but could result in erro-
neous data capture of some or all of the bits, especially at
higher sample rates and in marginally designed systems.
1.1.1 Calibration
A calibration is performed upon power-up and can also be
invoked by the user upon command. Calibration trims the 100
Ω analog input differential termination resistor and minimizes
full-scale error, offset error, DNL and INL, resulting in maxi-
mizing SNR, THD, SINAD (SNDR) and ENOB. Internal bias
currents are also set with the calibration process. All of this is
true whether the calibration is performed upon power up or is
performed upon command. Running the calibration is an im-
portant part of this chip's functionality and is required in order
to obtain adequate performance. In addition to the require-
ment to be run at power-up, an on-command calibration must
be run whenever the sense of the FSR pin is changed. For
best performance, we recommend that an on-command cal-
ibration be run 20 seconds or more after application of power
and whenever the operating temperature changes signifi-
cantly relative to the specific system performance require-
ments. See
information. Calibration can not be initiated or run while the
device is in the power-down mode. See
A
supply voltage will have the same effect as allowing it to
2.4.2.2 On-Command Calibration
1.1.7 Power Down
for more
for
26
information on the interaction between Power Down and Cal-
ibration.
In normal operation, calibration is performed just after appli-
cation of power and whenever a valid calibration command is
given, which is holding the CAL pin low for at least t
cycles, then hold it high for at least another t
as defined in the Converter Electrical Characteristics. The
time taken by the calibration procedure is specified as t
Converter Electrical Characteristics. Holding the CAL pin high
upon power up will prevent the calibration process from run-
ning until the CAL pin experiences the above-mentioned
t
CalDly (pin 127) is used to select one of two delay times that
apply from the application of power to the start of calibration.
This calibration delay time is depedent on the setting of the
CalDly pin and is specified as t
Characteristics. These delay values allow the power supply
to come up and stabilize before calibration takes place. If the
PD pin is high upon power-up, the calibration delay counter
will be disabled until the PD pin is brought low. Therefore,
holding the PD pin high during power up will further delay the
start of the power-up calibration cycle. The best setting of the
CalDly pin depends upon the power-on settling time of the
power supply.
The CAL bit does not reset itself to zero automatically, but
must be manually reset before another calibration event can
be initiated. If no further calibration event is desired, the CAL
bit may be left high indefinitely, with no negative conse-
quences. The RTD bit setting is critical for running a calibra-
tion event with the Clock Phase Adjust enabled. If initiating a
calibration event while the Clock Phase Adjust is enabled, the
RTD bit must be set to high, or no calibration will occur. If
initiating a calibration event while the Clock Phase Adjust is
not enabled, a normal calibration will occur, regardless of the
setting of the RTD bit.
1.1.2 Acquiring the Input
In 1:2 demux mode, data is acquired at the falling edge of CLK
+ (pin 18) and the digital equivalent of that data is available
at the digital outputs 13 input clock cycles later for the DI and
DQ output buses and 14 input clock cycles later for the DId
and DQd output buses. There is an additional internal delay
called t
Timing Diagram. The ADC08D1020 will convert as long as
the input clock signal is present. The fully differential com-
parator design and the innovative design of the sample-and-
hold amplifier, together with calibration, enables a very flat
SINAD/ENOB response beyond 1 GHz. The ADC08D1020
output data signaling is LVDS and the output format is offset
binary.
1.1.3 Control Modes
Much of the user control can be accomplished with several
control pins that are provided. Examples include initiation of
the calibration cycle, power down mode and full scale range
setting. However, the ADC08D1020 also provides an Extend-
ed Control mode whereby a serial interface is used to access
register-based control of several advanced features. The Ex-
tended Control mode is not intended to be enabled and
disabled dynamically. Rather, the user is expected to employ
either the normal control mode or the Extended Control mode
at all times. When the device is in the Extended Control mode,
pin-based control of several features is replaced with register-
based control and those pin-based controls are disabled.
These pins are OutV (pin 3), OutEdge/DDR (pin 4), FSR (pin
14) and CalDly/DES (pin 127). See
ED CONTROL
CAL_L
clock cycles followed by t
OD
before the data is available at the outputs. See the
for details on the Extended Control mode.
CalDly
CAL_H
in the Converter Electrical
1.2 NORMAL/EXTEND-
clock cycles.
CAL_H
clock cycles
CAL_L
clock
CAL
in