ADC08D1020DEV/NOPB National Semiconductor, ADC08D1020DEV/NOPB Datasheet - Page 29

• Manufacturer Part Number: ADC08D1020DEV/NOPB
• Description: BOARD DEV FOR ADC08D1020
• Manufacturer: National Semiconductor
• Series: PowerWise®r

Specifications of ADC08D1020DEV/NOPB

• Number Of Adc's: 2
• Number Of Bits: 8
• Sampling Rate (per Second): 1G
• Data Interface: Serial
• Inputs Per Adc: 1 Differential
• Input Range: 870 mVpp
• Power (typ) @ Conditions: 1.6W @ 1GSPS
• Voltage Supply Source: Single Supply
• Operating Temperature: -40°C ~ 85°C
• Utilized Ic / Part: ADC08D1020
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: ADC08D1020DEV

1.2 NORMAL/EXTENDED CONTROL
The ADC08D1020 may be operated in one of two modes. In
the simpler standard control mode, the user affects available
configuration and control of the device through several control
pins. The "extended control mode" provides additional con-
figuration and control options through a serial interface and a
set of 9 registers. Extended control mode is selected by set-
SDR or DDR Clocking
DDR Clock Phase
SDR Data transitions with rising
or falling DCLK edge
LVDS output level
Power-On Calibration Delay
Full-Scale Range
Input Offset Adjust
Dual Edge Sampling Selection Enabled with pin 127 floating
Dual Edge Sampling
Input Channel Selection
Test Pattern
Resistor Trim Disable
Selectable Output
Demultiplexer
Second DCLK Output
Sampling Clock Phase Adjust
Feature
Selected with pin 4
Not Selectable (0° Phase Only)
SDR Data transitions with rising
edge of DCLK+ when pin 4 is high
and on falling edge when low.
Normal differential data and DCLK
amplitude selected when pin 3 is
high and reduced amplitude
selected when low.
Short delay selected when pin 127 is
low and longer delay selected when
high.
Normal input full-scale range
selected when pin 14 is high and
reduced range when low. Selected
range applies to both channels.
Not possible
Only I-Channel Input can be used
Not possible
Not possible
Not possible
Not possible
Not possible
Normal Control Mode
TABLE 3. Features and Modes
29
ting pin 41 to logic low. If pin 41 is floating and pin 52 is floating
or logic high, pin 14 can be used to enable the extended con-
trol mode. The choice of control modes is required to be a
fixed selection and is not intended to be switched dynamically
while the device is operational.
Table 3
by the control mode chosen.
Selected with nDE in the Configuration Register
(Addr-1h; bit-10).
Selected with DCP in the Configuration Register
(Addr-1h; bit-11).
Selected with OED in the Configuration Register
(Addr-1h; bit-8).
Selected with OV in the Configuration Register
(Addr-1h; bit-9).
Short delay only.
Up to 512 step adjustments over a nominal range
specified in
range selected for I- and Q-Channels. Selected using
Full Range Registers (Addr-3h and Bh; bit-7 thru 15).
512 steps of adjustment using the Input Offset register
specified in
channel using Input Offset Registers (Addr-2h and Ah;
bit-7 thru 15).
Enabled by programming DES in the Extended
Configuration Register (Addr-9h; bit-13).
Either I- or Q-Channel input may be sampled by both
ADCs.
A test pattern can be made present at the data outputs
by setting TPO to 1b in Extended Configuration
Register (Addr-9h; bit-15).
The DCLK outputs will continuously be present when
RTD is set to 1b in Extended Configuration Register
(Addr-9h; bit-14 to 7).
If the device is set in DDR, the output can be
programmed to be non-demultiplex. When OED in
Configuration Register is set 1b (Addr-1h; bit-8), this
selects non-demultiplex. If OED is set 0b, this selects
1:2 demultiplex.
The OR outputs can be programmed to become a
second DCLK output when nSD is set 0b in
Configuration Register (Addr-1h; bit-13).
The sampling clock phase can be manually adjusted
through the Coarse and Intermediate Register (Addr-
Fh; bit-15–7) and Fine Register (Addr-Eh; bit-15 to 8).
shows how several of the device features are affected
1.4 REGISTER
1.4 REGISTER DESCRIPTION
Extended Control Mode
DESCRIPTION. Separate
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for each