ADC08D1020DEV/NOPB National Semiconductor, ADC08D1020DEV/NOPB Datasheet - Page 5

• Manufacturer Part Number: ADC08D1020DEV/NOPB
• Description: BOARD DEV FOR ADC08D1020
• Manufacturer: National Semiconductor
• Series: PowerWise®r

Specifications of ADC08D1020DEV/NOPB

• Number Of Adc's: 2
• Number Of Bits: 8
• Sampling Rate (per Second): 1G
• Data Interface: Serial
• Inputs Per Adc: 1 Differential
• Input Range: 870 mVpp
• Power (typ) @ Conditions: 1.6W @ 1GSPS
• Voltage Supply Source: Single Supply
• Operating Temperature: -40°C ~ 85°C
• Utilized Ic / Part: ADC08D1020
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: ADC08D1020DEV

Pin Functions
Pin No.
127
14
18
19
11
10
22
23
CalDly / DES / SCS
FSR/ALT_ECE/
DCLK_RST-
Symbol
V
V
CLK+
CLK−
V
V
IN
IN
IN
IN
Q+
Q−
I+
I−
Equivalent Circuit
5
Full Scale Range Select, Alternate Extended Control Enable
and DCLK_RST-. This pin has three functions. It can
conditionally control the ADC full-scale voltage, enable the
extended control mode, or become the negative polarity
signal of a differential pair in differential DCLK_RST mode.
If pin 52 and pin 41 are floating or at logic high, this pin can
be used to set the full-scale-range or can be used as an
alternate extended control enable pin . When used as the
FSR pin, a logic low on this pin sets the full-scale differential
input range to a reduced V
pin sets the full-scale differential input range to a higher V
input level. See Converter Electrical Characteristics. To
enable the extended control mode, whereby the serial
interface and control registers are employed, allow this pin
to float or connect it to a voltage equal to V
NORMAL/EXTENDED CONTROL
extended control mode. Note that pin 41 overrides the
extended control enable of this pin. When pin 52 is held at
logic low, this pin acts as the DCLK_RST- pin. When in
differential DCLK_RST mode, there is no pin-controlled FSR
and the full-scale-range is defaulted to the higher V
level.
Calibration Delay, Dual Edge Sampling and Serial Interface
Chip Select. With a logic high or low on pin 14, this pin
functions as Calibration Delay and sets the number of input
clock cycles after power up before calibration begins (See
1.1.1
enable pin for the serial interface input and the CalDly value
becomes "0" (short delay with no provision for a long power-
up calibration delay). When this pin is floating or connected
to a voltage equal to V
is selected where the "I" input is sampled at twice the input
clock rate and the "Q" input is ignored. See
Edge
LVDS Clock input pins for the ADC. The differential clock
signal must be a.c. coupled to these pins. The input signal is
sampled on the falling edge of CLK+. See
the Input
CLOCK INPUTS
Analog signal inputs to the ADC. The differential full-scale
input range of this input is programmable using the FSR pin
14 in normal mode and the Input Full-Scale Voltage Adjust
register in the extended control mode. Refer to the V
specification in the Converter Electrical Characteristics for
the full-scale input range in the normal mode. Refer to
REGISTER DESCRIPTION
the extended control mode.
Calibration). With pin 14 floating, this pin acts as the
Sampling.
for a description of acquiring the input and
for an overview of the clock inputs.
A
/2, DES (Dual Edge Sampling) mode
Description
IN
for the full-scale input range in
input level. A logic high on this
for information on the
1.1.2 Acquiring
A
1.1.5.1 Dual-
/2. See
www.national.com
IN
2.3 THE
1.2
IN
input
1.4
IN