ADC08D1020DEV/NOPB National Semiconductor, ADC08D1020DEV/NOPB Datasheet - Page 27

• Manufacturer Part Number: ADC08D1020DEV/NOPB
• Description: BOARD DEV FOR ADC08D1020
• Manufacturer: National Semiconductor
• Series: PowerWise®r

Specifications of ADC08D1020DEV/NOPB

• Number Of Adc's: 2
• Number Of Bits: 8
• Sampling Rate (per Second): 1G
• Data Interface: Serial
• Inputs Per Adc: 1 Differential
• Input Range: 870 mVpp
• Power (typ) @ Conditions: 1.6W @ 1GSPS
• Voltage Supply Source: Single Supply
• Operating Temperature: -40°C ~ 85°C
• Utilized Ic / Part: ADC08D1020
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: ADC08D1020DEV

1.1.4 The Analog Inputs
The ADC08D1020 must be driven with a differential input sig-
nal. Operation with a single-ended signal is not recommend-
ed. It is important that the inputs either be a.c. coupled to the
inputs with the V
V
to the V
used.
Two full-scale range settings are provided with pin 14 (FSR).
A high on pin 14 causes an input full-scale range setting of a
higher V
full-scale range setting of a reduced V
scale range setting operates equally on both ADCs.
In the Extended Control mode, programming the Input Full-
Scale Voltage Adjust register allows the input full-scale range
to be adjusted as described in
TION
1.1.5 Clocking
The ADC08D1020 must be driven with an a.c. coupled, dif-
ferential clock signal.
use of the clock input pins. A differential LVDS output clock is
available for use in latching the ADC output data into whatever
device is used to receive the data.
The ADC08D1020 offers input and output clocking options.
These options include a choice of Dual Edge Sampling (DES)
or "interleaved mode" where the ADC08D1020 performs as a
single device converting at twice the input clock rate, a choice
of which DCLK edge the output data transitions on, and a
choice of Single Data Rate (SDR) or Double Data Rate (DDR)
outputs.
The ADC08D1020 also has the option to use a duty cycle
corrected clock receiver as part of the input clock circuit. This
feature is enabled by default and provides improved ADC
clocking especially in the Dual-Edge Sampling mode (DES).
* Note that, in DES + normal mode, only the I Channel is sampled. In DES + extended control mode, I or Q channel can be sampled.
** Note that, in the non-demultiplexed mode, the DId and DQd outputs are disabled and are high impedance.
CMO
respect to fall of DCLK
(Always sourced with
pin left floating. An input common mode voltage equal
and
Data Outputs
CMO
IN
2.2 THE ANALOG
input level, while grounding pin 14 causes an input
DQd
output must be provided when d.c. coupling is
DId
DQ
DI
+)
TABLE 1. Input Channel Samples Produced at Data Outputs in 1:2 Demultiplexed Mode**
CMO
2.3 THE CLOCK INPUTS
pin grounded, or d.c. coupled with the
"I" Input Sampled with Fall of CLK 13
cycles earlier.
"I" Input Sampled with Fall of CLK 14
cycles earlier.
"Q" Input Sampled with Fall of CLK 13
cycles earlier.
"Q" Input Sampled with Fall of CLK 14
cycles after being sampled.
INPUT.
1.4 REGISTER DESCRIP-
Normal Sampling Mode
IN
input level. The full-
describes the
27
This circuitry allows the ADC to be clocked with a signal
source having a duty cycle ratio of 20% / 80% (worst case)
for both the normal and the Dual Edge Sampling modes.
1.1.5.1 Dual-Edge Sampling
The DES mode allows one of the ADC08D1020's inputs (I or
Q Channel) to be sampled by both ADCs. One ADC samples
the input on the positive edge of the input clock and the other
ADC samples the same input on the falling edge of the input
clock. A single input is thus sampled twice per input clock cy-
cle, resulting in an overall sample rate of twice the input clock
frequency, or 2 GSPS with a 1 GHz input clock.
In this mode, the outputs must be carefully interleaved to re-
construct the sampled signal. If the device is programmed into
the 1:2 demultiplex mode while in DES mode, the data is ef-
fectively demultiplexed 1:4. If the input clock is 1 GHz, the
effective sampling rate is doubled to 2 GSPS and each of the
4 output buses have a 500 MHz output rate. All data is avail-
able in parallel. To properly reconstruct the sampled wave-
form, the four bytes of parallel data that are output with each
clock are in the following sampling order from the earliest to
the latest and must be interleaved as such: DQd, DId, DQ, DI.
See
ious sampling possibilities. If the device is programmed into
the non-demultiplex mode, two bytes of parallel data are out-
put with each edge of the clock in the following sampling
order, from the earliest to the latest: DQ, DI. See
In the non-extended mode of operation only the "I" input can
be sampled in the DES mode. In the extended mode of op-
eration, the user can select which input is sampled.
The ADC08D1020 includes an automatic clock phase back-
ground adjustment which is used in DES mode to automati-
cally and continuously adjust the clock phase of the I and Q
channel. This feature provides optimal Dual-Edge Sampling
performance.
"I" Input Sampled with Fall of
CLK 13 cycles earlier.
"I" Input Sampled with Fall of
CLK 14 cycles earlier.
"I" Input Sampled with Rise
of CLK 13.5 cycles earlier.
"I" Input Sampled with Rise
of CLK 14.5 cycles earlier.
I-Channel Selected
Table 1
Dual-Edge Sampling Mode (DES)
indicates what the outputs represent for the var-
"Q" Input Sampled with Fall
of CLK 13 cycles earlier.
"Q" Input Sampled with Fall
of CLK 14 cycles earlier.
"Q" Input Sampled with Rise
of CLK 13.5 cycles earlier.
"Q" Input Sampled with Rise
of CLK 14.5 cycles earlier.
Q-Channel Selected *
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Table
2.