ADC08D1020DEV/NOPB National Semiconductor, ADC08D1020DEV/NOPB Datasheet - Page 31

• Manufacturer Part Number: ADC08D1020DEV/NOPB
• Description: BOARD DEV FOR ADC08D1020
• Manufacturer: National Semiconductor
• Series: PowerWise®r

Specifications of ADC08D1020DEV/NOPB

• Number Of Adc's: 2
• Number Of Bits: 8
• Sampling Rate (per Second): 1G
• Data Interface: Serial
• Inputs Per Adc: 1 Differential
• Input Range: 870 mVpp
• Power (typ) @ Conditions: 1.6W @ 1GSPS
• Voltage Supply Source: Single Supply
• Operating Temperature: -40°C ~ 85°C
• Utilized Ic / Part: ADC08D1020
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: ADC08D1020DEV

1.4 REGISTER DESCRIPTION
Nine write-only registers provide several control and config-
uration options in the Extended Control Mode. These regis-
ters have no effect when the device is in the Normal Control
Mode. Each register description below also shows the Power-
On Reset (POR) state of each control bit.
Bit 15
Bits 14:0
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Addr: 0h (0000b)
Addr: 1h (0001b)
CAL
D15
D15
D7
D7
1
1
1
D14
D14
D6
D6
1
1
0
1
CAL: Calibration Enable. When this bit is set
1b, an on-command calibration cycle is
initiated. This function is exactly the same as
issuing an on-command calibration using the
CAL pin.
POR State: 0b
Must be set to 1b
Must be set to 1b
Must be set to 0b
nSD: Second DCLK Output Enable. When
this bit is 1b, the device only has one DCLK
output and one OR output. When this bit is
0b, the device has two identical DCLK
outputs and no OR output.
POR State: 1b
DCS: Duty Cycle Stabilizer. When this bit is
set to 1b, a duty cycle stabilization circuit is
applied to the clock input. When this bit is set
to 0b the stabilization circuit is disabled.
POR State: 1b
DCP: DDR Clock Phase. This bit only has an
effect in the DDR mode. When this bit is set
to 0b, the DCLK edges are time-aligned with
the data bus edges ("0° Phase"). When this
bit is set to 1b, the DCLK edges are placed
in the middle of the data bit-cells ("90°
Phase"), using the one-half speed DCLK
shown in
POR State: 0b
D13
D13
nSD
Configuration Register
D5
D5
1
1
1
Calibration Register
Figure 4
DCS DCP
D12
D12
D4
D4
1
1
1
D11
D11
D3
D3
as the phase reference.
1
1
1
Write only (0xB2FF)
Write only (0x7FFF)
nDE
D10
D10
D2
D2
1
1
1
OV
D9
D1
D9
D1
1
1
1
OED
D8
D0
D8
D0
1
1
1
31
IMPORTANT NOTE: It is recommended that this register
should only be written upon power-up initialization as writing
it may cause disturbance on the DCLK output as this signal's
basic configuration is changed.
Bit 10
Bit 9
Bit 8
Bits 7:0
nDE: DDR Enable. When this bit is set to 0b,
data bus clocking follows the DDR (Double
Data Rate) mode whereby a data word is
output with each rising and falling edge of
DCLK. When this bit is set to a 1b, data bus
clocking follows the SDR (single data rate)
mode whereby each data word is output with
either the rising or falling edge of DCLK , as
determined by the OutEdge bit.
POR State: 0b
OV: Output Voltage. This bit determines the
LVDS outputs' voltage amplitude and has the
same function as the OutV pin that is used in
the normal control mode. When this bit is set
to 1b, the standard output amplitude of 710
mV
reduced output amplitude of 510 mV
used.
POR State: 1b
OED: Output Edge and Demultiplex Control.
This bit has two functions. When the device
is in SDR mode, this bit selects the DCLK
edge with which the data words transition
and has the same effect as the OutEdge pin
in the Non-extended control mode. When this
bit is set to 1b, the data outputs change with
the rising edge of DCLK+. When this bit is set
to 0b, the data output changes with the falling
edge of DCLK+. When the device is in DDR
mode, this bit selects the non-demultiplexed
mode when set to 1b. When the bit set to 0b,
the
Demultiplexed mode. If the device is in DDR
and Non-Demultiplexed Mode, then the
DCLK has a 0° phase relationship with the
data; it is not possible to select the 90° phase
relationship.
POR State: 0b
Must be set to 1b
P-P
device
is used. When this bit is set to 0b, the
is
programmed
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into
P-P
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