Z8F16800144ZCOG Zilog, Z8F16800144ZCOG Datasheet - Page 216

• Manufacturer Part Number: Z8F16800144ZCOG
• Description: KIT DEV FOR Z8F642 MCU 44 PIN
• Manufacturer: Zilog
• Series: Z8 Encore!®r
• Type: MCUr

Specifications of Z8F16800144ZCOG

• Contents: Hardware, Software and Documentation
• For Use With/related Products: Z8F642
• For Use With: 269-4661 - KIT ACC ETHERNET SMART CABLE
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 269-4678

PS025011-1010
From Master
From Master
From Master
When the ESPI is configured as a Master in a Multi-Master SPI system, the SS pin must
be configured as an input. The SS input signal on a device configured as a Master should
remain High. If the SS signal on the active Master goes Low (indicating another 
Master is accessing this device as a Slave), a Collision error flag is set in the ESPI Status
register. The Slave select outputs on a Master in a Multi-Master system must come from
GPIO pins.
SPI Slave Operation
The ESPI block is configured for SLAVE mode operation by setting the MMEN bit = 0 
in the ESPICTL register, and setting the SSIO bit = 0 in the ESPIMODE register. 
The SSMD field of the ESPI Mode register is set to 00 for SPI protocol mode. The
PHASE, CLKPOL, and WOR bits in the ESPICTL register and the NUMBITS 
field in the ESPIMODE register must be set to be consistent with the other 
SPI devices. Typically for an SPI Slave, SSPO = 0.
If the Slave has data to send to the Master, the data must be written to the Data 
register before the transaction starts (first edge of SCK when SS is asserted). 
If the Data register is not written prior to the Slave transaction, the MISO pin 
outputs all 1’s.
Due to the delay resulting from synchronization of the SS and SCK input signals to 
the internal system clock, the maximum SCK baud rate that can be supported in SLAVE
mode is the system clock frequency divided by 4. This rate is controlled by the 
SPI Master.
To Master
Figure 41
Figure 41. ESPI Configured as an SPI Slave
SS
MISO
MOSI
SCK
displays the ESPI configuration in SPI SLAVE mode.
P R E L I M I N A R Y
Bit 7
8-bit Shift Register
SPI Slave
Bit 0
Z8 Encore! XP
Enhanced Serial Peripheral Interface
Product Specification
®
F1680 Series
202