Z8F16800144ZCOG Zilog, Z8F16800144ZCOG Datasheet - Page 303

• Manufacturer Part Number: Z8F16800144ZCOG
• Description: KIT DEV FOR Z8F642 MCU 44 PIN
• Manufacturer: Zilog
• Series: Z8 Encore!®r
• Type: MCUr

Specifications of Z8F16800144ZCOG

• Contents: Hardware, Software and Documentation
• For Use With/related Products: Z8F642
• For Use With: 269-4661 - KIT ACC ETHERNET SMART CABLE
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 269-4678

PS025011-1010
High Speed Synchronous
The Auto-Baud Detector/Generator is clocked by the system clock. The minimum baud
rate is the system clock frequency divided by 512. If the data can be synchronized with the
system clock, the autobaud generator can run as high as the system clock frequency (1
clock / bit). The maximum recommended baud rate is the system clock frequency divided
by 8.
frequencies.
Table 162. OCD Baud-Rate Limits
If the OCD receives a Serial Break (ten or more continuous bits Low) the Auto-Baud
Detector/Generator resets. The Auto-Baud Detector/Generator can then be reconfigured
by sending 80H. If the Auto-Baud Detector overflows while measuring the Auto-Baud
character, the Auto-Baud Detector will remain reset.
It is possible to operate the serial On-Chip Debugger at high speeds. To operate at high
speeds, data must be synchronized with an external clock. High speed synchronous com-
munication will only work when using an external clock source. To operate in high speed
synchronous mode, simply Auto-Baud to the desired speed. The Auto-Baud generator will
automatically run at the desired baud rate.
Slow bus rise times due to the pullup resistor become a limiting factor when operating at
high speeds. To compensate for slow rise times, the output driver can be configured to
drive the line high. If the TXD (Transmit Drive) bit is set, the line will be driven both high
and low during transmission. The line starts being driven at the beginning of the start bit
and stops being driven at the middle of the stop bit. If the TXDH (Transmit Drive High)
bit is set, the line will be driven high until the input is high or the center of the bit occurs,
whichever is first. If both
period at the beginning of each 0 to 1 transition. An example of a high speed synchronous
interface is displayed in
System Clock
Frequency
20.0 MHz
1.0 MHz
32 kHz
Table 162
lists minimum and recommended maximum baud rates for sample crystal
Maximum Asynchronous
Baud Rate (bits/s)
2.5 M
125 k
4096
Figure
TXD
P R E L I M I N A R Y
and
60.
TXDH
are set, the pin will be driven high for one clock
Minimum Baud
Rate (bits/s)
39.1 k
1.96 k
64
Z8 Encore! XP
Product Specification
®
On-Chip Debugger
F1680 Series
289