Z8F16800144ZCOG Zilog, Z8F16800144ZCOG Datasheet - Page 217

• Manufacturer Part Number: Z8F16800144ZCOG
• Description: KIT DEV FOR Z8F642 MCU 44 PIN
• Manufacturer: Zilog
• Series: Z8 Encore!®r
• Type: MCUr

Specifications of Z8F16800144ZCOG

• Contents: Hardware, Software and Documentation
• For Use With/related Products: Z8F642
• For Use With: 269-4661 - KIT ACC ETHERNET SMART CABLE
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 269-4678

®
Z8 Encore! XP
F1680 Series
Product Specification
203
Error Detection
Error events detected by the ESPI block are described in this section. Error events
generate an ESPI interrupt and set a bit in the ESPI Status register. The error bits of the
ESPI Status register are Read/Write 1 to clear.
Transmit Underrun
A transmit underrun error occurs for a Master with SSMD = 10 or 11 when a character
transfer completes and TDRE = 1. In these modes when a transmit underrun occurs the
transfer will be aborted (SCK will halt and SSV will be deassertd). For a Master in SPI
mode (SSMD = 00), a transmit underrun is not signaled since SCK will pause and wait for
the data register to be written.
In SLAVE mode, a transmit underrun error occurs if TDRE = 1 at the start of a transfer.
When a transmit underrun occurs in SLAVE mode, ESPI will transmit a character|
of all 1s.
A transmit underrun sets the TUND bit in the ESPI Status register to 1. Writing a 1 to TUND
clears this error flag.
Mode Fault (Multi-Master Collision)
A mode fault indicates when more than one Master is trying to communicate
simultaneously (a Multi-Master collision) in SPI mode. The mode fault is detected when
the enabled Master’s SS input pin is asserted. For this to happen the Control and Mode
registers must be configured with MMEN = 1, SSIO = 0 (SS is an input), and SS input = 0.
A mode fault sets the COL bit in the ESPI Status register to 1. Writing a 1 to COL clears
this error flag.
Receive Overrun
A receive overrun error occurs when a transfer completes and the RDRNE bit is still set
from the previous transfer. A receive overrun sets the ROVR bit in the ESPI Status register
to 1. Writing a 1 to ROVR clears this error flag. The receive data register is not overwritten
and will contain the data from the transfer which initially set the RDRNE bit. Subsequent
received data is lost until the RDRNE bit is cleared.
In SPI MASTER mode, a receive overrun will not occur. Instead, the SCK will be paused
until software responds to the previous RDRNE/TDRE requests.
SLAVE Mode Abort
In SLAVE mode of operation, if the SS pin deasserts before all bits in a character have
been transferred, the transaction is aborted. When this condition occurs the ABT bit is set
in the ESPI Status register. A Slave abort error resets the Slave control logic to idle state.
A Slave abort error is also asserted in SLAVE mode, if BRGCTL = 1 and a baud rate
generator timeout occurs. When BRGCTL = 1 in Slave mode, the baud rate generator
PS025011-1010
P R E L I M I N A R Y
Enhanced Serial Peripheral Interface