IPT-C2H-NIOS Altera, IPT-C2H-NIOS Datasheet - Page 104

• Manufacturer Part Number: IPT-C2H-NIOS
• Description: C2H COMPILER FOR NIOS II
• Manufacturer: Altera
• Series: Nios®IIr
• Type: Nios IIr

Specifications of IPT-C2H-NIOS

• Function: C to Hardware Compiler
• License: Initial License
• Software Application: IP CORE, NIOS Processor And Functions
• Core Architecture: FPGA
• Core Sub-architecture: Cyclone
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: Not applicable / Not applicable

Performance
Performance
Example 4–2. CRC32 (Ethernet CRC)
#pragma altera_accelerate connect_variable\
#pragma altera_accelerate connect_variable\
unsigned long crc_calculation
{
}
4–10
Nios II C2H Compiler User Guide
( unsigned char * _ _ restrict_ _ data,
unsigned long i, crc = 0xFFFFFFFF;
unsigned char lut_addr;
for (i = 0; i < length; i++)
{
}
return (crc ^ 0xFFFFFFFF);
crc_calculation/data to onchipRAM1
crc_calculation/table to onchipRAM2
unsigned long * _ _ restrict_ _ table,
unsigned long length)
lut_addr = (crc & 0xFF) ^ *data++;
crc = (crc >> 8) ^ table[lut_addr];
The performance section of the C2H build report details information
about each loop in the accelerated function. For each loop shown, the
report contains the following information:
■
■
■
■
■
In the following discussion of information shown in the performance
section, refer to
Source Line Number
The performance section of the build report shows a source line number
for each loop statement. The line number is determined by the beginning
of the loop, which is the source line containing the opening block
delimiter ({). If your coding style places the loop keyword (do, while, or
for) on a separate line from the delimiter, the report shows the line where
the delimiter appears.
File name and source line number
Loop latency
Cycles per loop iteration (CPLI)
Scheduling information per assignment
Scheduling information per state
Example
9.1
4–2.
Altera Corporation
November 2009