IPT-C2H-NIOS Altera, IPT-C2H-NIOS Datasheet - Page 24

• Manufacturer Part Number: IPT-C2H-NIOS
• Description: C2H COMPILER FOR NIOS II
• Manufacturer: Altera
• Series: Nios®IIr
• Type: Nios IIr

Specifications of IPT-C2H-NIOS

• Function: C to Hardware Compiler
• License: Initial License
• Software Application: IP CORE, NIOS Processor And Functions
• Core Architecture: FPGA
• Core Sub-architecture: Cyclone
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: Not applicable / Not applicable

Typical Design Flow
Typical Design
Flow
2–2
Nios II C2H Compiler User Guide
f
A typical design flow using the C2H Compiler to accelerate a function
involves the following steps:
1.
2.
3.
4.
5.
6.
7.
8.
The typical C2H Compiler design flow is an iterative process of
accelerating a function, comparing the performance to design
requirements, and modifying C code to improve results. If you start with
C code that is not optimized for the C2H Compiler, the first iteration of
acceleration might not dramatically improve performance. Further
iterations, modifying the C code for optimal hardware structure, often
improve the final results significantly over the first pass results.
This tutorial does not describe techniques for optimizing hardware
accelerator performance. For further information on optimizing
C2H Compiler results, refer to the
C2H Compiler
Software Requirements
The C2H Compiler in evaluation mode is installed as part of the Altera
Quartus
Complete Design Suite free from the Altera website. Visit
www.altera.com
Develop and debug your application or algorithm in C targeting a
Nios II processor system.
Profile the code to identify the areas that would benefit from
hardware acceleration.
Isolate the code you want to accelerate into an individual C
function.
Specify the function you want to accelerate in the Nios II IDE.
Rebuild the project in the Nios II IDE.
Profile the results in hardware, or observe estimates from the C2H
report in the Nios II IDE.
If the results do not meet the design requirements, modify the C
source code and system architecture (for example, the memory
topology).
Return to Step 5, and iterate.
®
II Complete Design Suite. You can download the Quartus II
Tutorial.
and click Download.
9.1
Accelerating Nios II Systems with the
Altera Corporation
November 2009
®