IPT-C2H-NIOS Altera, IPT-C2H-NIOS Datasheet - Page 3

• Manufacturer Part Number: IPT-C2H-NIOS
• Description: C2H COMPILER FOR NIOS II
• Manufacturer: Altera
• Series: Nios®IIr
• Type: Nios IIr

Specifications of IPT-C2H-NIOS

• Function: C to Hardware Compiler
• License: Initial License
• Software Application: IP CORE, NIOS Processor And Functions
• Core Architecture: FPGA
• Core Sub-architecture: Cyclone
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: Not applicable / Not applicable

Chapter 1. Introduction to the C2H Compiler
Chapter 2. Getting Started Tutorial
Altera Corporation
User Guide Overview ........................................................................................................................... 1–1
Target Audience ..................................................................................................................................... 1–2
Introduction ............................................................................................................................................ 1–2
C2H Compiler Concepts ....................................................................................................................... 1–6
C Code Appropriate for Hardware Acceleration ........................................................................... 1–13
Next Steps ............................................................................................................................................. 1–16
Introduction ............................................................................................................................................ 2–1
C2H Compiler Design Flow ................................................................................................................. 2–1
Typical Design Flow .............................................................................................................................. 2–2
Tutorial .................................................................................................................................................... 2–4
Features .............................................................................................................................................. 1–2
Design Abstraction and the Rise of C for FPGAs ........................................................................ 1–3
What to Expect From the C2H Compiler ...................................................................................... 1–5
C2H Support in Nios II Tool Flows ............................................................................................... 1–6
Simplicity and Ease of Use .............................................................................................................. 1–6
Rapid Design Iteration to Find Optimal Partitioning of Hardware and Software ................. 1–7
Accelerate Performance-Critical Sections of Code ...................................................................... 1–7
The C2H Compiler Operates at the Function Level .................................................................... 1–8
System Architecture ......................................................................................................................... 1–9
Generation of a Hardware Accelerator ....................................................................................... 1–10
One-to-One Mapping From C Syntax to Hardware Structure ................................................ 1–11
Performance Depends on Memory Access Time ....................................................................... 1–12
Ideal Acceleration Candidates ...................................................................................................... 1–13
Poor Acceleration Candidates ...................................................................................................... 1–14
Understanding Code to Find Opportunities for Acceleration ................................................. 1–15
Starting Point for the C2H Compiler Design Flow ..................................................................... 2–1
Software Requirements ................................................................................................................... 2–2
OpenCore Plus Evaluation .............................................................................................................. 2–3
Tutorial Design ................................................................................................................................. 2–4
Set up the Hardware for the Project .............................................................................................. 2–5
Create the Software Project ............................................................................................................. 2–6
Run the Project as Software Only .................................................................................................. 2–7
Create and Configure a Hardware Accelerator ........................................................................... 2–8
Rebuild the Project ......................................................................................................................... 2–10
Observe Results in the Report File ............................................................................................... 2–11
Observe the Accelerator in SOPC Builder .................................................................................. 2–14
Run the Project with the Accelerator ........................................................................................... 2–14
Remove the Accelerator ................................................................................................................ 2–15
9.1
Contents
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