IPT-C2H-NIOS Altera, IPT-C2H-NIOS Datasheet - Page 86

• Manufacturer Part Number: IPT-C2H-NIOS
• Description: C2H COMPILER FOR NIOS II
• Manufacturer: Altera
• Series: Nios®IIr
• Type: Nios IIr

Specifications of IPT-C2H-NIOS

• Function: C to Hardware Compiler
• License: Initial License
• Software Application: IP CORE, NIOS Processor And Functions
• Core Architecture: FPGA
• Core Sub-architecture: Cyclone
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: Not applicable / Not applicable

Scheduling
Figure 3–23. Pipelined Loop Iterations with a Loop-Carried Dependency
3–46
Nios II C2H Compiler User Guide
Figure 3–23
iterations of the loop shown in
imposed by hash. State 1 cannot execute until the previous iteration has
completed State 2. The C2H Compiler schedules the states as shown in
Figure 3–23
In
straight arrows between iterations.
Pipelining Avalon-MM Read Transfers from Multiple Iterations
As discussed in section
the C2H Compiler is aware of read latency in slave memories. Master
ports on C2H accelerators can use Avalon-MM pipelined read transfers,
which allow multiple read transfers to be pending at a given time. As a
result, for a loop that reads from memory with latency, the next iteration
of the loop can begin fetching data before data from the previous iteration
has returned. For such a loop, the C2H Compiler creates a master port
Figure
3–23, the cyclic arrow for hash in
illustrates how the C2H Compiler schedules successive
to satisfy the loop-carried dependency.
9.1
“Read Operations with Latency” on page
Figure
3–22, based on the restrictions
Figure 3–22
Altera Corporation
translates to
November 2009
3–37,