ADV212-ASD-P160-EB Analog Devices Inc, ADV212-ASD-P160-EB Datasheet
ADV212-ASD-P160-EB
Specifications of ADV212-ASD-P160-EB
Related parts for ADV212-ASD-P160-EB
ADV212-ASD-P160-EB Summary of contents
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... The ADV212 is an upgrade version of the ADV202, which is identical in pinout and footprint. It supports all of the func- tionality of the ADV202 and has the following additional options: JTAG/boundary scan support and power reduction of at least 30% compared with the ADV202 ...
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... Changes to Video Interface (VDATA Bus) Section, Changes to Table 17 ............................................................................................ 26 Changes to Hardware Boot Modes Section ................................ 31 Changes to Encode—Multichip Mode Section .......................... 34 Memory System .......................................................................... 25 Internal DMA Engine ................................................................ 25 ADV212 Interfaces ......................................................................... 26 Video Interface (VDATA Bus) .................................................. 26 Host Interface (HDATA Bus) ................................................... 26 Direct and Indirect Registers .................................................... 26 Control Access Registers ........................................................... 27 Pin Configuration and Bus Sizes/Modes ................................ 27 Stage Register ...
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... The ADV212 can process images at a rate of 40 MSPS in reversible mode and at higher rates when used in irreversible mode. The ADV212 contains a dedicated wavelet transform engine, three entropy CODECs, an on-board memory system, and an embedded reduced instruction set computer (RISC) processor that can provide a complete JPEG2000 compression/ decompression solution ...
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... Dynamic Current, Core (JCLK 2 Frequency = 81 MHz) Dynamic Current, Input/Output No clock or input/output activity For a definition of JCLK, see Figure 32. 3 ADV212-150 only. INPUT/OUTPUT SPECIFICATIONS Table 2. Parameter High Level Input Voltage Low Level Input Voltage High Level Output Voltage Low Level Output Voltage High Level Input Current ...
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... MCLK t 6 MCLKL t 6 MCLKH t 13.4 VCLK f 20 VCLK t 5 VCLKL t 5 VCLKH t 5 RESET t MCLK t t MCLKL MCLKH t VCLK t t VCLKL VCLKH Figure 2. Input Clock Rev Page Typ Max Unit 100 ns 75.18 MHz 74.60 MHz ns ns MCLK cycles ADV212 1 ...
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... ADV212 NORMAL HOST MODE—WRITE OPERATION Table 4. Parameter WE to ACK, Direct Registers and FIFO Accesses WE to ACK, Indirect Registers Data Setup Data Hold Address Setup Address Hold Setup CS Hold Write Inactive Pulse Width (Minimum Time Until Next WE Pulse) Write Active Pulse Width ...
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... JCLK RH t 2.5 JCLK RL t 5.0 JCLK RCYC RCYC ACK t t DRD HZRD VALID Figure 4. Normal Host Mode—Read Operation Rev Page ADV212 Typ Max 1.5 × JCLK + 7 15.5 × JCLK + 7.0 2 1.5 × JCLK + 7 15.5 × JCLK + 7 Unit ...
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... ADV212 DREQ/DACK DMA MODE—SINGLE FIFO WRITE OPERATION Table 6. Parameter DREQ Pulse Width DACK Assert to Subsequent DREQ Delay WE to DACK Setup Data to DACK Deassert Setup Data to DACK Deassert Hold DACK Assert Pulse Width DACK Deassert Pulse Width WE Hold After DACK Deassert WE Assert to FSRQ Deassert (FIFO Full) DACK to DREQ Deassert (DR × ...
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... LOW DACK WEFB HDATA Figure 7. Single Write Cycle for Fly-By DMA Mode ( DREQ Pulse Width Is Programmable) FCS0 RD FIFO NOT FULL FSRQ0 0 HDATA Figure 8. Single Write Access for DCS DMA Mode HIGH 1 2 WFSRQ 1 Rev Page ADV212 FIFO FULL 2 NOT WRITTEN TO FIFO ...
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... ADV212 DREQ/DACK DMA MODE—SINGLE FIFO READ OPERATION Table 7. Parameter DREQ Pulse Width DACK Assert to Subsequent DREQ Delay RD to DACK Setup DACK to Data Valid Data Hold DACK Assert Pulse Width DACK Deassert Pulse Width RD Hold after DACK Deassert RD Assert to FSRQ Deassert (FIFO Empty) DACK to DREQ Deassert (DR × ...
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... DREQ DACK DACK LOW DACK RDFB t RD HDATA 0 Figure 11. Single Read Cycle for Fly-By DMA Mode ( DREQ Pulse Width Is Programmable) FCS0 RD FIFO NOT EMPTY FSRQ0 HDATA Figure 12. Single Read Access for DCS DMA Mode HIGH RDFSRQ FIFO EMPTY 1 Rev Page ADV212 ...
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... ADV212 EXTERNAL DMA MODE—FIFO WRITE, BURST MODE Table 8. Parameter DREQ Pulse Width DREQ Deassert (DR × PULS = 0) DACK to WE Setup Data Setup Data Hold WE Assert Pulse Width WE Deassert Pulse Width WE Deassert to Next DREQ WE Deassert to DACK Deassert 1 Applies to assigned DMA channel, if EDMOD0/EDMOD1[14:11] is programmed to a nonzero value. ...
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... Programmed to a Value of 0000) t DREQ RTN t DACK Figure 18. Burst Read Cycle for Fly-By DMA Mode Rev Page Typ Max 2 15 JCLK 2 2 3.5 × JCLK + 7 3.5 × JCLK + 7 DREQ WAIT t RD_DACK DREQ WAIT t RD_DACK DREQ WAIT t RD_DACK 14 15 ADV212 Unit ...
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... ADV212 STREAMING MODE (JDATA)—FIFO READ/WRITE Table 10. Parameter MCLK to JDATA Valid MCLK to VALID Assert/Deassert HOLD Setup to Rising MCLK HOLD Hold from Rising MCLK JDATA Setup to Rising MCLK JDATA Hold from Rising MCLK 1 For a definition of JCLK, see Figure 32. MCLK JDATA TD JDATA VALID ...
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... Figure 21. Encode Video Mode Timing—CCIR 656 Mode HSYNC Figure 22. Encode Video Mode Timing—HVF Mode (HSYNC Timing) (HSYNC Programmed for Negative Polarity) VSYNC SU (VSYNC and FIELD Programmed for Negative Polarity) Rev Page Min Typ Max Unit VCLK cycles VCLK cycles 00 SAV HSYNC VSYNC HD FIELD HD ADV212 ...
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... ADV212 VCLK VDATA TD VDATA (OUT) HSYNC (IN) VSYNC (IN) FIELD (IN) VCLK VDATA TD VDATA (OUT) HSYNC (IN) VSYNC (IN) FIELD (IN) VCLK VDATA (OUT) HSYNC (OUT) VSYNC (OUT) FIELD TD FIELD (OUT) Figure 26. Decode Video Mode Timing—CCIR 656 Mode, Decode Master VCLK VDATA (OUT) HSYNC (OUT) VSYNC (OUT) ...
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... RAW PIXEL MODE—ENCODE TD PIXEL 1 PIXEL 2 VFRM TD VRDY TD RAW PIXEL MODE—DECODE Figure 28. Raw Pixel Modes Rev Page Mnemonic Min Typ VDATA TD VDATA 4 SU VDATA 4 HD VRDY TD VFRM 3 SU VFRM 4 HD VFRM TD VSTRB 4 SU VSTRB 3 HD VSTRB HD PIXEL 3 VSTRB HD ADV212 Max Unit ...
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... ADV212 JTAG TIMING Table 13. Parameter TCK Period TDI or TMS Setup Time TDI or TMS Hold Time TDO Hold Time TDO Valid TRS Hold Time TRS Setup Time TRS Pulse Width Low TCK TDO TDI TMS TRS Mnemonic Min TCK 134 TDI 4.0 ...
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... THERMAL RESISTANCE θ is specified for the worst-case conditions, that is, a device JA soldered in a circuit board for surface-mount packages. Table 15. Thermal Resistance Package Type 144-Ball ADV212BBCZ 121-Ball ADV212BBCZ ESD CAUTION Rev Page ADV212 θ θ Unit ...
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... Type Description I System Input Clock. See the PLL Registers section. I Reset. Causes the ADV212 to immediately reset. CS, RD, WE, DACK0, DACK1, DREQ0, and DREQ1 must be held high when a RESET is applied. I/O Host Data Bus. With HDATA[23:16], HDATA[27:24], and HDATA[31:28], these pins make up the 32-bit wide host data bus. The async host interface is interfaced together with ADDR[3:0], CS, WE, RD, and ACK ...
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... ADV212. The interrupt sources are enabled via the bits in the EIRQIE register. O Data Request for External DMA Interface. Indicates that the ADV212 is ready to send/receive data to/from the FIFO assigned to DMA Channel 0. O FIFO Service Request. Used in DCS-DMA mode ...
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... This pin should be tied low via a 10 kΩ resistor. I/O Serial Communication. This pin must be used in multiple chip mode to align the outputs of two or more ADV212s. For details, see the Applications Information section. used, this pin should be tied low via a 10 kΩ resistor. ...
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... I JTAG Serial Data Input. If JTAG is used, connect a 10 kΩ pull-up resistor to this pin. If JTAG is not used, this pin should be connected to ground via a pull-down resistor. O JTAG Serial Data Output. If this pin is not used, do not connect it. V Positive Supply for Core. ADV212 ...
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... In encode mode with fly-by DMA, the host can use the RDFB signal ( WE pin) to simultaneously read from the ADV212 and write to an external device such as memory decode mode with fly-by DMA, the host can use the WEFB signal ( RD pin) to simultaneously read from the external device and write to the ADV212. ...
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... THEORY OF OPERATION The input video or pixel data is passed to the ADV212 pixel interface, and samples are deinterleaved and passed to the wavelet engine, which decomposes each tile or frame into subbands using the 5/3 or 9/7 filters. The resultant wavelet coefficients are then written to the internal memory. The entropy CODECs code the image data so that it conforms to the JPEG2000 standard ...
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... The default bus mode uses the same pins to transfer control, status, and data to and from the ADV212. In this mode, the ADV212 can support 16- and 32-bit control transfers and 8-/16-/32-bit data transfers. The size of these buses can be selected independ- ...
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... The bus is always an output during compression operations and an input during decompression. A 2-pin handshake is used to transfer data over this synchron- ous interface. VALID is used to indicate that the ADV212 is ready to provide or accept data and is always an output. HOLD is always an input and is asserted by the host if it cannot accept/ provide data ...
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... ADV212 INTERNAL REGISTERS This section describes the internal registers of the ADV212. DIRECT REGISTERS The ADV212 has 16 direct registers, as listed in Table 18. Table 18. Direct Registers Address Name 0x00 Pixel 0x01 Code 0x02 ATTR 0x03 Reserved 0x04 CMDSTA 0x05 EIRQIE 0x06 EIRQFLG 0x07 SWFLAG ...
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... Pixel Mode 2 VMODE Video mode EDMOD0 External DMA Mode Register 0 EDMOD1 External DMA Mode Register 1 FFTHRP FIFO threshold for pixel FIFO Reserved Reserved Reserved Reserved FFTHRC FIFO threshold for code FIFO FFTHRA FIFO threshold for ATTR FIFO Reserved Reserved Rev Page ADV212 ...
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... If this delay is not implemented, erratic behavior may result. MCLK is the input clock to the ADV212 PLL and is used to generate the internal JCLK (JPEG2000 processor clock) and HCLK (embedded CPU clock). ...
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... CFG1 is tied to IOVDD through resistor and CFG2 is tied to GND through resistor. There is no special power sequencing requirement for VDD and IOVDD strongly recommended that the user place a small decoup- ling cap close to every power pin and at least one bulk cap on each supply. Rev Page ADV212 ...
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... ADV212 VIDEO INPUT FORMATS The ADV212 supports a wide variety of formats for uncom- pressed video and still image data. The actual interface and bus modes selected for transferring uncompressed data dictates the allowed size of the input data and the number of samples transferred with each access. ...
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... Table 24. Maximum Supported Tile Width for Data Input on HDATA and VDATA Buses Compression Mode 9/7i 9/7i 9/7i 5/3i 5/3i 5/3i 5/3r 5/3r 5/3r Input Format Single-component Two-component Three-component Single-component Two-component Three-component Single-component Two-component Three-component Rev Page Tile/Precinct Maximum Width 2048 1024 each 1024 (Y) 4096 2048 (each) 2048 (Y) 4096 2048 1024 ADV212 ...
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... ADV212 JPEG2000 video processor. ENCODE—MULTICHIP MODE Due to the data input rate limitation (see Table 22), an 1080i application requires at least two ADV212s to encode or decode full-resolution 1080i video. In encode mode, the ADV212 accepts Y and CbCr data on separate buses. An encode example is shown in Figure 33. ...
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... IRQ DREQ DACK In a slave/slave configuration, the common HVF for both ADV212s is generated by an external house sync, and each SCOMM5 is connected to the same GPIO output on the host. SWIRQ1, Software Interrupt 1 in the EIRQIE register, must be unmasked on both devices to enable multichip mode. ...
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... DIGITAL STILL CAMERA/CAMCORDER Figure typical configuration for a digital camera or camcorder. AD9843A 10 D[9:0] SDATA SCK SL Figure 35. Digital Still Camera/Camcorder Encode Application for 10-Bit Pixel Data Using Raw Pixel Mode ADV212 FPGA MCLK DATA INPUTS[9:0] VCLK VFRM SERIAL DATA VRDY SERIAL CLK VSTRB ...
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... ENCODE/DECODE SDTV VIDEO APPLICATION Figure 36 shows two ADV212 chips using a 10-bit CCIR 656 in normal host mode. ENCODE MODE 32-BIT HOST CPU DATA[31:0] ADDR[3:0] DECODE MODE 32-BIT HOST CPU DATA[31:0] ADDR[3:0] ADV212 VDATA[11:2] VCLK HDATA[31:0] 27MHz MCLK INTR IRQ OSC ADDR[3: ACK ...
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... ADV212 32-BIT HOST APPLICATION Figure 37 shows two ADV212 chips using a 10-bit CCIR 656 in normal host mode. FPGA DATA[31:0] 32-BIT HOST CPU DATA[31:0] ADDR[3:0] FPGA DATA[31:0] 31-BIT HOST CPU DATA[31:0] ADDR[3:0] ADV212 DREQ0 DREQ0 DACK0 DACK0 VDATA[11:2] HDATA[31:0] VCLK 27MHz MCLK OSC ...
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... HDATA<4> Cr0/G3<3> HDATA<3> Cr0/G3<2> HDATA<2> Cr0/G3<1> HDATA<1> Cr0/G3<0> HDATA<0> DATA<31:0> ACK ACK IRQ IRQ DREQ DREQ0 DACK DACK0 DREQ DREQ1 DACK DACK1 74.25MHz MCLK Figure 38. Host Interface—Pixel Interface Mode Rev Page ADV212 COMPRESSED DATA PATH RAW PIXEL DATA PATH ADV212 ...
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... ADV212 JDATA INTERFACE Figure 39 shows a typical configuration using JDATA with a dedicated JDATA output, 16-bit host, and 10-bit CCIR 656. FPGA 16-BIT HOST CPU DATA[15:0] ADDR[3:0] ADV212 YCrCb JDATA[7:0] VDATA[11:2] HOLD FIELD VALID VSYNC HSYNC VCLK HDATA[15:0] IRQ IRQ ADDR[3:0] 27MHz MCLK ...
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... EXCEPTION TO PACKAGE HEIGHT AND THICKNESS. Figure 41. 144-Ball Chip Scale Package Ball Grid Array [CSP_BGA] (BC-144-3) Dimensions shown in millimeters Rev Page CORNER INDEX AREA 1.31 1.21 1.11 0.20 COPLANARITY SEATING PLANE A1 CORNER INDEX AREA 1.32 1.21 1.11 COPLANARITY 0.20 MAX SEATING PLANE ADV212 ...
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... Temperature Model 1 Range ADV212BBCZ-115 −40°C to +85°C ADV212BBCZRL-115 −40°C to +85°C ADV212BBCZ-150 −40°C to +85°C ADV212BBCZRL-150 −40°C to +85° RoHS Compliant Part. Speed Grade Operating Voltage Package Description 115 MHz 1.5 V Internal, 121-Ball Chip Scale Package Ball Grid Array [CSP_BGA] 2 ...
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... NOTES Rev Page ADV212 ...
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... ADV212 NOTES ©2006–2010 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D06389-0-4/10(B) Rev Page ...