ADV212-ASD-P160-EB Analog Devices Inc, ADV212-ASD-P160-EB Datasheet - Page 22

• Manufacturer Part Number: ADV212-ASD-P160-EB
• Description: BOARD EVAL FOR ADV212 CODEC
• Manufacturer: Analog Devices Inc

Specifications of ADV212-ASD-P160-EB

• Module/board Type: Evaluation Board
• For Use With/related Products: ADV212
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

ADV212
Pin No.
65
75
90 to 92, 78
79 to 81, 70
69, 68,
59, 58
57, 46 to 48
112
113
114
100
121-Ball Package
Location
F10
G9
J2 to J4, H1
H2 to H4, G4
G3, G2,
F4, F3
F2, E2, E3,
E4
L2
L3
L4
K1
Pin No.
70
69
111, 97 to
99
100, 85 to
87
88, 73 to 75
76, 61 to 63
134
135
136
121
144-Ball Package
Location
F10
F9
K3, J1 to J3
J4, H1 to H3
H4, G1 to G3
G4, F1 to F3
M2
M3
M4
L1
Mnemonic
DREQ1
FSRQ1
CFG2
DACK1
FCS1
HDATA[31:28]
JDATA[7:4]
HDATA[27:24]
JDATA[3:0]
HDATA[23:20]
HDATA[19:16]
VDATA[15:12]
SCOMM7
SCOMM6
SCOMM5
SCOMM4
Rev. B | Page 22 of 44
Pins
Used
1
1
4
4
4
4
8
Type
O
O
I
I
I
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
O
Description
Data Request for External DMA Interface.
Indicates that the ADV212 is ready to
send/receive data to/from the FIFO assigned
to DMA Channel 1.
FIFO Service Request. Used in DCS-DMA
mode. Service request from the FIFO assigned
to Channel 1 (asynchronous mode).
Boot Mode Configuration. This pin is read on
reset to determine the boot configuration of
the on-board processor. The pin should be
tied to DGND through a 10 kΩ resistor.
Data Acknowledge for External DMA Interface.
Signal from the host CPU, which indicates that
the data transfer request (DREQ1) has been
acknowledged and data transfer can proceed.
This pin must be held high at all times unless
a DMA or JDATA access is occurring. This pin
must be held high at all times if the DMA
interface is not used, even if the DMA
channels are disabled.
FIFO Chip Select. Used in DCS-DMA mode.
Chip select for the FIFO assigned to Channel 1
(asynchronous mode).
Host Expansion Bus.
JDATA Bus (JDATA Mode).
Host Expansion Bus.
JDATA Bus (JDATA Mode).
Host Expansion Bus.
Host Expansion Bus.
Video Data. Used only for raw pixel video
mode. Unused pins should be pulled down via
a 10 kΩ resistor.
Serial Communication. For internal use only.
This pin should be tied low via a 10 kΩ
resistor.
Serial Communication. For internal use only.
This pin should be tied low via a 10 kΩ
resistor.
Serial Communication. This pin must be used
in multiple chip mode to align the outputs of
two or more ADV212s. For details, see the
Applications Information
used, this pin should be tied low via a 10 kΩ
resistor.
LCODE Output in Encode Mode. When LCODE
is enabled, the output on this pin indicates on
a high transition that the last data-word for a
field has been read from the FIFO. For an 8-bit
interface, such as JDATA, LCODE is asserted for
four consecutive bytes and is enabled
by default.
section.
When not