ADV212-ASD-P160-EB Analog Devices Inc, ADV212-ASD-P160-EB Datasheet - Page 8

• Manufacturer Part Number: ADV212-ASD-P160-EB
• Description: BOARD EVAL FOR ADV212 CODEC
• Manufacturer: Analog Devices Inc

Specifications of ADV212-ASD-P160-EB

• Module/board Type: Evaluation Board
• For Use With/related Products: ADV212
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

ADV212
DREQ/DACK DMA MODE—SINGLE FIFO WRITE OPERATION
Table 6.
Parameter
DREQ Pulse Width
DACK Assert to Subsequent DREQ Delay
WE to DACK Setup
Data to DACK Deassert Setup
Data to DACK Deassert Hold
DACK Assert Pulse Width
DACK Deassert Pulse Width
WE Hold After DACK Deassert
WE Assert to FSRQ Deassert (FIFO Full)
DACK to DREQ Deassert (DR × PULS = 0)
1
For a definition of JCLK, see Figure 32.
HDATA
HDATA
DREQ
DACK
DREQ
DACK
WE
WE
DREQ
t
t
WE
WE
Figure 5. Single Write for DREQ / DACK DMA Mode for Assigned DMA Channel
Figure 6. Single Write for DREQ / DACK DMA Mode for Assigned DMA Channel
SU
SU
PULSE
(EDMOD0/EDMOD1[14:1] Not Programmed to a Value of 0000)
DACK
DACK
(EDMOD0/EDMOD1[14:11] Programmed to a Value of 0000)
t
t
LOW
LOW
SU
SU
t
t
DREQ
DREQ
0
0
DACK
DACK
t
t
RTN
HD
HD
HIGH
HIGH
Mnemonic
DREQ
t
t
t
t
DACK
DACK
t
WFSRQ
t
Rev. B | Page 8 of 44
DREQ
WE SU
SU
HD
WE HD
DREQ RTN
1
PULSE
LOW
HIGH
1
Min
1 JCLK
2.5 JCLK
0
2
2
2 JCLK
2 JCLK
0
1.5 JCLK
2.5 JCLK
2
1
1
1
1
1
1
2
Typ
t
t
WE
WE
HD
HD
Max
15 JCLK
3.5 × JCLK + 8.5
2.5 × JCLK + 7.5
3.5 × JCLK + 9.0
3
1
1
1
1
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns