ADV212-ASD-P160-EB Analog Devices Inc, ADV212-ASD-P160-EB Datasheet - Page 13

• Manufacturer Part Number: ADV212-ASD-P160-EB
• Description: BOARD EVAL FOR ADV212 CODEC
• Manufacturer: Analog Devices Inc

Specifications of ADV212-ASD-P160-EB

• Module/board Type: Evaluation Board
• For Use With/related Products: ADV212
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

EXTERNAL DMA MODE—FIFO READ, BURST MODE
Table 9.
Parameter
DREQ Pulse Width
RD to DREQ Deassert (DR × PULS = 0)
DACK to RD Setup
RD to Data Valid
Data Hold
RD Assert Pulse Width
RD Deassert Pulse Width
RD Deassert to Next DREQ
RD Deassert to DACK Deassert
1
2
Applies to assigned DMA channel if EDMOD0 or EDMOD1 <14:11> is programmed to a nonzero value.
For a definition of JCLK, see Figure 32.
HDATA
HDATA
HDATA
DREQ
DACK
DREQ
DACK
DREQ
DACK
RDFB
1
RD
RD
Figure 16. Burst Read Cycle for DREQ / DACK DMA Mode for Assigned DMA Channel
Figure 17. Burst Read Cycle for DREQ / DACK DMA Mode for Assigned DMA Channel
t
DREQ
t
t
RD
RD
PULSE
t
t
DREQ
t
DACK
DACK
0
0
t
t
t
HD
(EMOD0/EDMOD1[14:11] Programmed to a Value of 0000)
(EMOD0/EDMOD1[14:11] Not Programmed to a Value of 0
DACK
HD
0
RTN
SU
SU
t
t
DREQ
RD
SU
Figure 18. Burst Read Cycle for Fly-By DMA Mode
RTN
t
HD
1
1
1
RD
Mnemonic
DREQ
t
t
t
t
RD
RD
t
t
DREQ RTN
DACK SU
RD
HD
DREQ WAIT
RD_DACK
RD
LOW
Rev. B | Page 13 of 44
LOW
HIGH
LOW
PULSE
13
13
13
RD
RD
HIGH
Min
1 JCLK
2.5 JCLK
0
2.5
2.5
1.5 JCLK
1.5 JCLK
2.5 JCLK
0
HIGH
14
14
14
t
RD_DACK
t
RD_DACK
2
t
RD_DACK
2
2
2
2
15
15
15
Typ
t
DREQ
t
DREQ
Max
15 JCLK
3.5 × JCLK + 7.5
9.7
3.5 × JCLK + 7.5
WAIT
WAIT
t
DREQ
2
WAIT
2
2
ADV212
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns