PIC12F519-I/MC Microchip Technology, PIC12F519-I/MC Datasheet - Page 47

• Manufacturer Part Number: PIC12F519-I/MC
• Description: IC PIC MCU FLASH 1KX12 8DFN
• Manufacturer: Microchip Technology
• Series: PIC® 12Fr

Specifications of PIC12F519-I/MC

• Core Size: 8-Bit
• Program Memory Size: 1.5KB (1K x 12)
• Core Processor: PIC
• Speed: 8MHz
• Peripherals: POR, WDT
• Number Of I /o: 5
• Program Memory Type: FLASH
• Ram Size: 41 x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 8-DFN
• Controller Family/series: PIC12
• No. Of I/o's: 6
• Eeprom Memory Size: 64Byte
• Ram Memory Size: 41Byte
• Cpu Speed: 8MHz
• No. Of Timers: 1
• Package: 8DFN EP
• Device Core: PIC
• Family Name: PIC12
• Maximum Speed: 8 MHz
• Operating Supply Voltage: 2.5|3.3|5 V
• Data Bus Width: 8 Bit
• Number Of Programmable I/os: 6
• Interface Type: USB
• Number Of Timers: 1
• Processor Series: PIC12F
• Core: PIC
• Data Ram Size: 41 B
• Maximum Clock Frequency: 8 MHz
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC164334 - MODULE SOCKET FOR 8L 2X3MM DFNXLT08DFN2 - SOCKET TRANSITION ICE 14DIP/8DFN
• Eeprom Size: -
• Data Converters: -
• Connectivity: -
• Lead Free Status / Rohs Status: Details

8.5
On the PIC12F519 device, the DRT runs any time the
device is powered up. DRT runs from Reset and varies
based on oscillator selection and Reset type (see
Table 8-5).
The DRT operates on an internal RC oscillator. The
processor is kept in Reset as long as the DRT is active.
The DRT delay allows V
for the oscillator to stabilize.
Oscillator circuits based on crystals or ceramic
resonators require a certain time after power-up to
establish a stable oscillation. The on-chip DRT keeps
the devices in a Reset condition after MCLR has
reached a logic high (V
GP3/MCLR/V
network connected to the MCLR input is not required in
most cases. This allows savings in cost-sensitive and/or
space restricted applications, as well as allowing the
use of the GP3/MCLR/V
input.
The Device Reset Time delays will vary from
chip-to-chip due to V
variation. See AC parameters for details.
The DRT will also be triggered upon a Watchdog Timer
time-out from Sleep. This is particularly important for
applications using the WDT to wake from Sleep mode
automatically.
Reset sources are POR, MCLR, WDT time-out and
wake-up on pin change. See Section 8.8.2 “Wake-up
from Sleep”, Notes 1, 2 and 3.
TABLE 8-5:
© 2008 Microchip Technology Inc.
INTOSC, EXTRC
LP, XT
Configuration
Oscillator
Device Reset Timer (DRT)
PP
as MCLR and using an external RC
DRT (DEVICE RESET TIMER
PERIOD)
18 ms (typical)
1 ms (typical)
POR Reset
DD
DD
IH
PP
, temperature and process
MCLR) level. Programming
to rise above V
pin as a general purpose
18 ms (typical)
10 μs (typical)
Subsequent
DD
Resets
min. and
8.6
The Watchdog Timer (WDT) is a free running on-chip
RC oscillator, which does not require any external
components. This RC oscillator is separate from the
external RC oscillator of the (GP5)/OSC1/CLKIN pin
and the internal 4 or 8 MHz oscillator. This means that
the WDT will run even if the main processor clock has
been stopped, for example, by execution of a SLEEP
instruction. During normal operation or Sleep, a WDT
Reset or wake-up Reset, generates a device Reset.
The TO bit (STATUS<4>) will be cleared upon a
Watchdog Timer Reset.
The
programming the configuration WDTE as a ‘0’ (see
Section 8.1 “Configuration Bits”). Refer to the
PIC12F519 Programming Specification (DS41316) to
determine how to access the Configuration Word.
8.6.1
The WDT has a nominal time-out period of 18 ms, (with
no prescaler). If a longer time-out period is desired, a
prescaler with a division ratio of up to 1:128 can be
assigned to the WDT (under software control) by writing
to the OPTION register. Thus, a time-out period of a
nominal 2.3 seconds can be realized. These periods
vary with temperature, V
variations (see DC specs).
Under worst-case conditions (V
= Max., max. WDT prescaler), it may take several
seconds before a WDT time-out occurs.
8.6.2
The CLRWDT instruction clears the WDT and the
postscaler, if assigned to the WDT, and prevents it from
timing out and generating a device Reset.
The SLEEP instruction resets the WDT and the
postscaler, if assigned to the WDT. This gives the
maximum Sleep time before a WDT wake-up Reset.
WDT
Watchdog Timer (WDT)
WDT PERIOD
WDT PROGRAMMING
CONSIDERATIONS
can
be
DD
permanently
PIC12F519
and part-to-part process
DD
= Min., Temperature
DS41319B-page 45
disabled
by