PIC16F1938-I/ML Microchip Technology, PIC16F1938-I/ML Datasheet - Page 123

• Manufacturer Part Number: PIC16F1938-I/ML
• Description: IC MCU 8BIT FLASH 28QFN
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 16Fr

Specifications of PIC16F1938-I/ML

• Core Size: 8-Bit
• Program Memory Size: 28KB (16K x 14)
• Oscillator Type: Internal
• Core Processor: PIC
• Speed: 32MHz
• Connectivity: I²C, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LCD, POR, PWM, WDT
• Number Of I /o: 25
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 11x10b
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-VQFN Exposed Pad, 28-HVQFN, 28-SQFN, 28-DHVQFN
• Controller Family/series: PIC16F
• No. Of I/o's: 25
• Eeprom Memory Size: 256Byte
• Ram Memory Size: 1024Byte
• Cpu Speed: 32MHz
• Package: 28QFN EP
• Device Core: PIC
• Family Name: PIC16
• Maximum Speed: 32 MHz
• Operating Supply Voltage: 2.5|3.3|5 V
• Data Bus Width: 8 Bit
• Number Of Programmable I/os: 25
• Interface Type: I2C/SPI/USART
• On-chip Adc: 11-chx10-bit
• Number Of Timers: 5
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

9.0
The module consists of a single SR Latch with multiple
Set and Reset inputs as well as separate latch outputs.
The SR Latch module includes the following features:
• Programmable input selection
• SR Latch output is available internally/externally
• Separate Q and Q outputs
• Firmware Set and Reset
9.1
The latch is a Set-Reset latch that does not depend on a
clock source. Each of the Set and Reset inputs are
active-high. The latch can be Set or Reset by CxOUT,
SRI pin, or variable clock. Additionally the SRPS and the
SRPR bits of the SRCON0 register may be used to Set
or Reset the SR Latch, respectively. The latch is
Reset-dominant, therefore, if both Set and Reset inputs
are high the latch will go to the Reset state. Both the
SRPS and SRPR bits are self resetting which means
that a single write to either of the bits is all that is
necessary to complete a latch Set or Reset operation.
FIGURE 9-1:
© 2009 Microchip Technology Inc.
SRI
SR LATCH
Latch Operation
SRI
SYNCC2OUT
SYNCC1OUT
SYNCC2OUT
SYNCC1OUT
SRPS
SRPR
Note 1:
SRRCKE
SRSCKE
SRRC1E
SRSC1E
SRRC2E
SRSC2E
SRRPE
SRSPE
SRCLK
SRCLK
2:
3:
SR LATCH SIMPLIFIED BLOCK DIAGRAM
(3)
(3)
(3)
(3)
If R = 1 and S = 1 simultaneously, Q = 0, Q = 1
Pulse generator causes a 1 Q-state pulse width.
Name denotes the connection point at the comparator output.
Gen
Gen
Pulse
Pulse
(2)
(2)
Preliminary
9.2
The SRQEN and SRNQEN bits of the SRCON0 regis-
ter control the Q and Q latch outputs. Both of the SR
latch outputs may be directly output to an I/O pin at the
same time.
The applicable TRIS bit of the corresponding port must
be cleared to enable the port pin output driver.
9.3
Upon any device Reset, the SR latch is not initialized.
The user’s firmware is responsible to initialize the latch
output before enabling it to the output pins.
PIC16F193X/LF193X
SR
Latch
S
R
SRNQEN
SRQEN
SRLEN
SRLEN
Latch Output
Effects of a Reset
(1)
Q
Q
DS41364C-page 123
SRNQ
SRQ