PIC16F1938-I/ML Microchip Technology, PIC16F1938-I/ML Datasheet - Page 59

• Manufacturer Part Number: PIC16F1938-I/ML
• Description: IC MCU 8BIT FLASH 28QFN
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 16Fr

Specifications of PIC16F1938-I/ML

• Core Size: 8-Bit
• Program Memory Size: 28KB (16K x 14)
• Oscillator Type: Internal
• Core Processor: PIC
• Speed: 32MHz
• Connectivity: I²C, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LCD, POR, PWM, WDT
• Number Of I /o: 25
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 11x10b
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-VQFN Exposed Pad, 28-HVQFN, 28-SQFN, 28-DHVQFN
• Controller Family/series: PIC16F
• No. Of I/o's: 25
• Eeprom Memory Size: 256Byte
• Ram Memory Size: 1024Byte
• Cpu Speed: 32MHz
• Package: 28QFN EP
• Device Core: PIC
• Family Name: PIC16
• Maximum Speed: 32 MHz
• Operating Supply Voltage: 2.5|3.3|5 V
• Data Bus Width: 8 Bit
• Number Of Programmable I/os: 25
• Interface Type: I2C/SPI/USART
• On-chip Adc: 11-chx10-bit
• Number Of Timers: 5
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

3.0
The
various kinds of Reset:
a)
b)
c)
d)
e)
f)
g)
Some registers are not affected in any Reset condition;
their status is unknown on POR and unchanged in any
other Reset. Most other registers are reset to a “Reset
state” on:
• Power-on Reset (POR)
• MCLR Reset
• WDT Reset
• Brown-out Reset (BOR)
FIGURE 3-1:
© 2009 Microchip Technology Inc.
OSC1
MCLR
V
Power-on Reset (POR)
WDT Reset during normal operation
MCLR Reset
Brown-out Reset (BOR)
RESET instruction
Stack Overflow
Stack Underflow
Note 1: See Table 3-5 for time-out situations.
DD
PIC16F193X/LF193X
RESETS
2: PWRT and OST counters are reset by POR and BOR.
Instruction
LFINTOSC
RESET
OST/PWRT
Pointer
Stack
Brown-out
Time-out
V
Detect
Sleep
DD
WDT
Reset
Rise
SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT
OST
Stack Full/Underflow Reset
External Reset
PWRT
MCLRE
10-bit Ripple Counter
11-bit Ripple Counter
(2)
POR Pulse
Enable
BOR
(2)
differentiates
1024 Cycles
64 ms
between
Preliminary
Most registers are not affected by a WDT wake-up
since this is viewed as the resumption of normal
operation. TO and PD bits are set or cleared differently
in different Reset situations, as indicated in Table 3-6.
These bits are used in software to determine the nature
of the Reset.
A simplified block diagram of the On-Chip Reset Circuit
is shown in Figure 3-1.
The MCLR Reset path has a noise filter to detect and
ignore small pulses. See Section 28.0 “Electrical
Specifications” for pulse width specifications.
PIC16F193X/LF193X
S
R
DS41364C-page 59
Q
Enable OST
Enable PWRT
Chip_Reset
(1)