ATTINY88-MU Atmel, ATTINY88-MU Datasheet - Page 11
![MCU AVR 8K ISP FLASH 1.8V 32-QFN](/photos/12/13/121310/attiny88-mu_sml.jpg)
ATTINY88-MU
Manufacturer Part Number
ATTINY88-MU
Description
MCU AVR 8K ISP FLASH 1.8V 32-QFN
Manufacturer
Atmel
Series
AVR® ATtinyr
Specifications of ATTINY88-MU
Core Processor
AVR
Core Size
8-Bit
Speed
12MHz
Connectivity
I²C, SPI
Peripherals
Brown-out Detect/Reset, POR, WDT
Number Of I /o
28
Program Memory Size
8KB (4K x 16)
Program Memory Type
FLASH
Eeprom Size
64 x 8
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
32-VQFN Exposed Pad, 32-HVQFN, 32-SQFN, 32-DHVQFN
Processor Series
ATTINY8x
Core
AVR8
Data Bus Width
8 bit
Data Ram Size
512 B
Interface Type
2-Wire, I2S, SPI
Maximum Clock Frequency
12 MHz
Number Of Programmable I/os
28
Number Of Timers
2
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWAVR, EWAVR-BL
Development Tools By Supplier
ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT, ATQT600, ATAVRTS2080B
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 8 Channel
Package
32QFN EP
Device Core
AVR
Family Name
ATtiny
Maximum Speed
12 MHz
Operating Supply Voltage
2.5|3.3|5 V
Cpu Family
ATtiny
Device Core Size
8b
Frequency (max)
12MHz
Total Internal Ram Size
512Byte
# I/os (max)
28
Number Of Timers - General Purpose
2
Operating Supply Voltage (typ)
2.5/3.3/5V
Operating Supply Voltage (max)
5.5V
Operating Supply Voltage (min)
1.8V
Instruction Set Architecture
RISC
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
32
Package Type
QFN EP
For Use With
ATSTK600-DIP40 - STK600 SOCKET/ADAPTER 40-PDIPATAVRDRAGON - KIT DRAGON 32KB FLASH MEM AVR
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ATTINY88-MU
Manufacturer:
ATMEL
Quantity:
21 342
Part Number:
ATTINY88-MU
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
Part Number:
ATTINY88-MUR
Manufacturer:
AT
Quantity:
20 000
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- Download datasheet (9Mb)
4.5.1
4.6
8008G–AVR–04/11
Stack Pointer
The X-register, Y-register, and Z-register
As shown in
directly into the first 32 locations of the user Data Space. Although not being physically imple-
mented as SRAM locations, this memory organization provides great flexibility in access of the
registers, as the X-, Y- and Z-pointer registers can be set to index any register in the file.
The registers R26:R31 have some added functions to their general purpose usage. These regis-
ters are 16-bit address pointers for indirect addressing of the data space. The three indirect
address registers X, Y, and Z are defined as described in
Figure 4-3.
In the different addressing modes these address registers have functions as fixed displacement,
automatic increment, and automatic decrement (see the instruction set reference for details).
The stack is mainly used for storing temporary data, local variables and return addresses after
interrupts and subroutine calls. The Stack Pointer registers (SPH and SPL) always point to the
top of the stack. Note that the stack grows from higher memory locations to lower memory loca-
tions. This means that the PUSH instructions decreases and the POP instruction increases the
stack pointer value.
The stack pointer points to the area of data memory where subroutine and interrupt stacks are
located. This stack space must be defined by the program before any subroutine calls are exe-
cuted or interrupts are enabled.
The pointer is decremented by one when data is put on the stack with the PUSH instruction, and
incremented by one when data is fetched with the POP instruction. It is decremented by two
when the return address is put on the stack by a subroutine call or a jump to an interrupt service
routine, and incremented by two when data is fetched by a return from subroutine (the RET
instruction) or a return from interrupt service routine (the RETI instruction).
The AVR stack pointer is typically implemented as two 8-bit registers in the I/O register file. The
width of the stack pointer and the number of bits implemented is device dependent. In some
X-register
Y-register
Z-register
Figure
The X-, Y-, and Z-registers
4-2, each register is also assigned a data memory address, mapping them
15
7
15
7
15
7
R27
R29
R31
XH
YH
ZH
0
0
0
Figure
7
7
7
4-3.
ATtiny48/88
R26
R28
R30
XL
YL
ZL
11
0
0
0
0
0
0
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