ATTINY88-MU Atmel, ATTINY88-MU Datasheet - Page 62
![MCU AVR 8K ISP FLASH 1.8V 32-QFN](/photos/12/13/121310/attiny88-mu_sml.jpg)
ATTINY88-MU
Manufacturer Part Number
ATTINY88-MU
Description
MCU AVR 8K ISP FLASH 1.8V 32-QFN
Manufacturer
Atmel
Series
AVR® ATtinyr
Specifications of ATTINY88-MU
Core Processor
AVR
Core Size
8-Bit
Speed
12MHz
Connectivity
I²C, SPI
Peripherals
Brown-out Detect/Reset, POR, WDT
Number Of I /o
28
Program Memory Size
8KB (4K x 16)
Program Memory Type
FLASH
Eeprom Size
64 x 8
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
32-VQFN Exposed Pad, 32-HVQFN, 32-SQFN, 32-DHVQFN
Processor Series
ATTINY8x
Core
AVR8
Data Bus Width
8 bit
Data Ram Size
512 B
Interface Type
2-Wire, I2S, SPI
Maximum Clock Frequency
12 MHz
Number Of Programmable I/os
28
Number Of Timers
2
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWAVR, EWAVR-BL
Development Tools By Supplier
ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT, ATQT600, ATAVRTS2080B
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 8 Channel
Package
32QFN EP
Device Core
AVR
Family Name
ATtiny
Maximum Speed
12 MHz
Operating Supply Voltage
2.5|3.3|5 V
Cpu Family
ATtiny
Device Core Size
8b
Frequency (max)
12MHz
Total Internal Ram Size
512Byte
# I/os (max)
28
Number Of Timers - General Purpose
2
Operating Supply Voltage (typ)
2.5/3.3/5V
Operating Supply Voltage (max)
5.5V
Operating Supply Voltage (min)
1.8V
Instruction Set Architecture
RISC
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
32
Package Type
QFN EP
For Use With
ATSTK600-DIP40 - STK600 SOCKET/ADAPTER 40-PDIPATAVRDRAGON - KIT DRAGON 32KB FLASH MEM AVR
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ATTINY88-MU
Manufacturer:
ATMEL
Quantity:
21 342
Part Number:
ATTINY88-MU
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
Part Number:
ATTINY88-MUR
Manufacturer:
AT
Quantity:
20 000
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10.2.2
10.2.3
10.2.4
62
ATtiny48/88
Toggling the Pin
Break-Before-Make Switching
Switching Between Input and Output
If PORTxn is written logic one when the pin is configured as an output pin, the port pin is driven
high (one). If PORTxn is written logic zero when the pin is configured as an output pin, the port
pin is driven low (zero).
Writing a logic one to PINxn toggles the value of PORTxn, independent on the value of DDRxn.
Note that the SBI instruction can be used to toggle one single bit in a port.
In the Break-Before-Make mode when switching the DDRxn bit from input to output an immedi-
ate tri-state period lasting one system clock cycle is introduced as indicated in
example, if the system clock is 4 MHz and the DDRxn is written to make an output, the immedi-
ate tri-state period of 250 ns is introduced, before the value of PORTxn is seen on the port pin.
To avoid glitches it is recommended that the maximum DDRxn toggle frequency is two system
clock cycles. The Break-Before-Make is a port-wise mode and it is activated by the port-wise
BBMx enable bits. For details on BBMx bits, see
When switching the DDRxn bit from output to input there is no immediate tri-state period
introduced.
Figure 10-3. Break Before Make, switching between input and output
When switching between tri-state ({DDxn, PORTxn} = 0b00) and output high ({DDxn, PORTxn}
= 0b11), an intermediate state with either pull-up enabled {DDxn, PORTxn} = 0b01) or output
low ({DDxn, PORTxn} = 0b10) must occur. Normally, the pull-up enabled state is fully accept-
able, as a high-impedant environment will not notice the difference between a strong high driver
and a pull-up. If this is not the case, the PUD bit in the MCUCR Register can be set to disable all
pull-ups in all ports.
Switching between input with pull-up and output low generates the same problem. The user
must use either the tri-state ({DDxn, PORTxn} = 0b00) or the output high state ({DDxn, PORTxn}
= 0b11) as an intermediate step.
INSTRUCTIONS
SYSTEM CLK
PORTx
DDRx
R17
R16
Px0
Px1
0x01
tri-state
out DDRx, r16
intermediate tri-state cycle
0x02
tri-state
nop
0x02
0x01
0x55
“PORTCR – Port Control Register” on page
out DDRx, r17
intermediate tri-state cycle
tri-state
0x01
Figure
8008G–AVR–04/11
10-3. For
77.
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