ATTINY88-MU Atmel, ATTINY88-MU Datasheet - Page 36

• Manufacturer Part Number: ATTINY88-MU
• Description: MCU AVR 8K ISP FLASH 1.8V 32-QFN
• Manufacturer: Atmel
• Series: AVR® ATtinyr

Specifications of ATTINY88-MU

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 12MHz
• Connectivity: I²C, SPI
• Peripherals: Brown-out Detect/Reset, POR, WDT
• Number Of I /o: 28
• Program Memory Size: 8KB (4K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 64 x 8
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-VQFN Exposed Pad, 32-HVQFN, 32-SQFN, 32-DHVQFN
• Processor Series: ATTINY8x
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 512 B
• Interface Type: 2-Wire, I2S, SPI
• Maximum Clock Frequency: 12 MHz
• Number Of Programmable I/os: 28
• Number Of Timers: 2
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT, ATQT600, ATAVRTS2080B
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• Package: 32QFN EP
• Device Core: AVR
• Family Name: ATtiny
• Maximum Speed: 12 MHz
• Operating Supply Voltage: 2.5|3.3|5 V
• Cpu Family: ATtiny
• Device Core Size: 8b
• Frequency (max): 12MHz
• Total Internal Ram Size: 512Byte
• # I/os (max): 28
• Number Of Timers - General Purpose: 2
• Operating Supply Voltage (typ): 2.5/3.3/5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 1.8V
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 32
• Package Type: QFN EP
• For Use With: ATSTK600-DIP40 - STK600 SOCKET/ADAPTER 40-PDIPATAVRDRAGON - KIT DRAGON 32KB FLASH MEM AVR
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

7. Power Management and Sleep Modes
7.1
7.1.1
36
Sleep Modes
ATtiny48/88
Idle Mode
Sleep modes enable the application to shut down unused modules in the MCU, thereby saving
power. The AVR provides various sleep modes allowing the user to tailor the power consump-
tion to the application’s requirements.
When enabled, the Brown-out Detector (BOD) actively monitors the power supply voltage during
the sleep periods. To further save power, it is possible to disable the BOD in some sleep modes.
See
Figure 6-1 on page 28
tion. The figure is helpful in selecting an appropriate sleep mode.
sleep modes, their wake up sources and the BOD disable ability.
Table 7-1.
Notes:
To enter any of the sleep modes, the SE bit in SMCR must be written to logic one and a SLEEP
instruction must be executed. The SM1, and SM0 bits in the SMCR Register select which sleep
mode (Idle, ADC Noise Reduction, or Power-down) will be activated by the SLEEP instruction.
See
If an enabled interrupt occurs while the MCU is in a sleep mode, the MCU wakes up. The MCU
is then halted for four cycles in addition to the start-up time, executes the interrupt routine, and
resumes execution from the instruction following SLEEP. The contents of the Register File and
SRAM are unaltered when the device wakes up from sleep. If a reset occurs during sleep mode,
the MCU wakes up and executes from the Reset Vector.
Note that if a level triggered interrupt is used for wake-up the changed level must be held for
some time to wake up the MCU (and for the MCU to enter the interrupt service routine). See
“External Interrupts” on page 53
When the SM[1:0] bits are written to 00, the SLEEP instruction makes the MCU enter Idle mode,
stopping the CPU but allowing the SPI, Analog Comparator, ADC, 2-wire Serial Interface,
Timer/Counters, Watchdog, and the interrupt system to continue operating. This sleep mode
basically halts clk
Sleep Mode
Idle
ADC Noise Reduction
Power-down
“Software BOD Disable” on page 37
Table 7-2 on page 39
1. For INT1 and INT0, only level interrupt
Active Clock Domains and Wake-up Sources in the Different Sleep Modes
CPU
and clk
presents the different clock systems in the ATtiny48/88, and their distribu-
Active Clock Domain
for a summary.
FLASH
for details.
, while allowing the other clocks to run.
X
for more details.
X
X
Oscillator
X
X
X
X
X
(1)
(1)
Table 7-1
X
X
X
Wake-up Source
X
X
shows the different
X
X
8008G–AVR–04/11
X
X
X
X