PIC16C770-I/SO Microchip Technology, PIC16C770-I/SO Datasheet - Page 85

• Manufacturer Part Number: PIC16C770-I/SO
• Description: IC MCU OTP 2KX14 A/D PWM 20-SOIC
• Manufacturer: Microchip Technology
• Series: PIC® 16Cr

Specifications of PIC16C770-I/SO

• Core Size: 8-Bit
• Program Memory Size: 3.5KB (2K x 14)
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Core Processor: PIC
• Speed: 20MHz
• Connectivity: I²C, SPI
• Number Of I /o: 15
• Program Memory Type: OTP
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 5.5 V
• Data Converters: A/D 6x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 20-SOIC (7.5mm Width)
• Controller Family/series: PIC16C
• No. Of I/o's: 16
• Ram Memory Size: 256Byte
• Cpu Speed: 20MHz
• No. Of Timers: 3
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: ISPICR1 - ADAPTER IN-CIRCUIT PROGRAMMINGAC164028 - MODULE SKT PROMATEII 20SOIC/DIP309-1013 - ADAPTER 20-SOIC TO 20-DIP309-1012 - ADAPTER 20-SOIC TO 20-DIP
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: PIC16C770I/SO

9.2.4
While in SLEEP mode, the I
receive addresses or data. When an address match or
complete byte transfer occurs, it wakes the processor
from SLEEP (if the SSP interrupt bit is enabled).
9.2.5
A RESET disables the MSSP module and terminates
the current transfer.
FIGURE 9-13:
2002 Microchip Technology Inc.
SDA
SCL
SLEEP OPERATION
EFFECTS OF A RESET
MSSP BLOCK DIAGRAM (I
SDA in
Bus Collision
SCL in
2
C slave module can
Read
Advance Information
MSb
START bit, STOP bit,
Write collision detect
START bit detect,
end of XMIT/RCV
Clock Arbitration
State counter for
STOP bit detect
Acknowledge
Generate
SSPBUF
SSPSR
2
C MASTER MODE)
LSb
Write
9.2.6
Master mode operation supports interrupt generation
on the detection of the START and STOP conditions.
The STOP (P) and START (S) bits are cleared from a
RESET or when the MSSP module is disabled. Control
of the I
bus is idle with both the S and P bits clear.
In Master mode, the SCL and SDA lines are manipu-
lated by the MSSP hardware.
The following events will cause SSP Interrupt Flag bit
(SSPIF) to be set (SSP Interrupt, if enabled):
• START condition
• STOP condition
• Data transfer byte transmitted/received
• Acknowledge transmit
• Repeated START
Clock
Data Bus
Shift
Internal
PIC16C717/770/771
Set/RESET, S, P, WCOL (SSPSTAT)
Set SSPIF, BCLIF
RESET ACKSTAT, PEN (SSPCON2)
2
C bus may be taken when the P bit is set or the
MASTER MODE
SSPADD<6:0>
SSPM<3:0>,
Baud
Rate
Generator
DS41120B-page 83