PIC16LF88-I/P Microchip Technology, PIC16LF88-I/P Datasheet - Page 91
![IC MCU FLASH 4KX14 EEPROM 18DIP](/photos/6/76/67657/18-dip_300mil__sml.jpg)
PIC16LF88-I/P
Manufacturer Part Number
PIC16LF88-I/P
Description
IC MCU FLASH 4KX14 EEPROM 18DIP
Manufacturer
Microchip Technology
Series
PIC® 16Fr
Datasheets
1.PIC16LF627A-IP.pdf
(8 pages)
2.PIC16F818-ISO.pdf
(6 pages)
3.PIC16F87-IP.pdf
(228 pages)
4.PIC16F87-IP.pdf
(8 pages)
5.PIC16F87-IP.pdf
(4 pages)
6.PIC16F87-IP.pdf
(8 pages)
7.PIC16F88-ISO.pdf
(214 pages)
Specifications of PIC16LF88-I/P
Program Memory Type
FLASH
Program Memory Size
7KB (4K x 14)
Package / Case
18-DIP (0.300", 7.62mm)
Core Processor
PIC
Core Size
8-Bit
Speed
10MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
16
Eeprom Size
256 x 8
Ram Size
368 x 8
Voltage - Supply (vcc/vdd)
2 V ~ 5.5 V
Data Converters
A/D 7x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
PIC16LF
Core
PIC
Data Bus Width
8 bit
Data Ram Size
368 B
Interface Type
SSP/USART
Maximum Clock Frequency
20 MHz
Number Of Programmable I/os
16
Number Of Timers
3
Operating Supply Voltage
2 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
Through Hole
3rd Party Development Tools
52715-96, 52716-328, 52717-734
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, DM163014
Minimum Operating Temperature
- 40 C
On-chip Adc
7-ch x 10-bit
Package
18PDIP
Device Core
PIC
Family Name
PIC16
Maximum Speed
20 MHz
Data Rom Size
256 B
Height
3.3 mm
Length
22.86 mm
Supply Voltage (max)
5.5 V
Supply Voltage (min)
2 V
Width
6.35 mm
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC16LF88-I/P
Manufacturer:
Microchip
Quantity:
1 302
REGISTER 10-2:
2003 Microchip Technology Inc.
bit 7
bit 6
bit 5
bit 4
bit 3-0
bit 7
WCOL: Write Collision Detect bit
1 = An attempt to write the SSPBUF register failed because the SSP module is busy
0 = No collision
SSPOV: Receive Overflow Indicator bit
In SPI mode:
1 = A new byte is received while the SSPBUF register is still holding the previous data. In case
0 = No overflow
In I
1 = A byte is received while the SSPBUF register is still holding the previous byte. SSPOV is a
0 = No overflow
SSPEN: Synchronous Serial Port Enable bit
In SPI mode:
1 = Enables serial port and configures SCK, SDO, and SDI as serial port pins
0 = Disables serial port and configures these pins as I/O port pins
In I
1 = Enables the serial port and configures the SDA and SCL pins as serial port pins
0 = Disables serial port and configures these pins as I/O port pins
CKP: Clock Polarity Select bit
In SPI mode:
1 = Transmit happens on falling edge, receive on rising edge. IDLE state for clock is a high level.
0 = Transmit happens on rising edge, receive on falling edge. IDLE state for clock is a low level.
In I
SCK release control
1 = Enable clock
0 = Holds clock low (clock stretch). (Used to ensure data setup time.)
SSPM<3:0>: Synchronous Serial Port Mode Select bits
0000 = SPI Master mode, clock = OSC/4
0001 = SPI Master mode, clock = OSC/16
0010 = SPI Master mode, clock = OSC/64
0011 = SPI Master mode, clock = TMR2 output/2
0100 = SPI Slave mode, clock = SCK pin. SS pin control enabled.
0101 = SPI Slave mode, clock = SCK pin. SS pin control disabled. SS can be used as I/O pin.
0110 = I
0111 = I
1011 = I
1110 = I
1111 = I
1000, 1001, 1010, 1100, 1101 = Reserved
Legend:
R = Readable bit
- n = Value at POR
SSPCON: SYNCHRONOUS SERIAL PORT CONTROL REGISTER (ADDRESS 14h)
WCOL
R/W-0
Note 1: In both modes, when enabled, these pins must be properly configured as input or
2
2
2
C mode:
C mode:
C Slave mode:
(must be cleared in software)
of overflow, the data in SSPSR is lost. Overflow can only occur in Slave mode. The user
must read the SSPBUF, even if only transmitting data, to avoid setting overflow. In Master
mode, the overflow bit is not set since each new reception (and transmission) is initiated by
writing to the SSPBUF register.
“don’t care” in Transmit mode. SSPOV must be cleared in software in either mode.
2
2
2
2
2
C Slave mode, 7-bit address
C Slave mode, 10-bit address
C firmware controlled Master mode (Slave IDLE)
C Slave mode, 7-bit address with START and STOP bit interrupts enabled
C Slave mode, 10-bit address with START and STOP bit interrupts enabled
output.
SSPOV
R/W-0
SSPEN
R/W-0
W = Writable bit
‘1’ = Bit is set
Preliminary
(1)
R/W-0
CKP
(1)
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
SSPM3
R/W-0
SSPM2
PIC16F87/88
R/W-0
x = Bit is unknown
SSPM1
R/W-0
DS30487B-page 89
SSPM0
R/W-0
bit 0