PIC18F67J90-I/PT Microchip Technology, PIC18F67J90-I/PT Datasheet - Page 334

• Manufacturer Part Number: PIC18F67J90-I/PT
• Description: IC PIC MCU FLASH 128KB 64-TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F67J90-I/PT

• Core Size: 8-Bit
• Program Memory Size: 128KB (64K x 16)
• Core Processor: PIC
• Speed: 48MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LCD, LVD, POR, PWM, WDT
• Number Of I /o: 51
• Program Memory Type: FLASH
• Ram Size: 3.8K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-TFQFP
• Controller Family/series: PIC18
• No. Of I/o's: 51
• Ram Memory Size: 3.8310546875KB
• Cpu Speed: 48MHz
• No. Of Timers: 4
• No. Of Pwm Channels: 2
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 3923 B
• Interface Type: AUSART, EUSART, I2C, SPI
• Maximum Clock Frequency: 48 MHz
• Number Of Programmable I/os: 51
• Number Of Timers: 4
• Operating Supply Voltage: 2.65 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 12 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC162079 - HEADER MPLAB ICD2 18F85J90 64/80AC164328 - MODULE SKT FOR 80TQFP
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

PIC18F87J90 FAMILY
25.3.2
When the on-chip regulator is enabled, PIC18F87J90
family devices also have a simple Brown-out Reset
capability. If the voltage supplied to the regulator falls to
a level that is inadequate to maintain a regulated output
for full-speed operation, the regulator Reset circuitry
will generate a Brown-out Reset. This event is captured
by the BOR flag bit (RCON<0>).
The operation of the BOR is described in more detail in
Section 5.4
Section 5.4.1 “Detecting BOR”.
25.3.3
The on-chip regulator is designed to meet the power-up
requirements for the device. If the application does not
use the regulator, then strict power-up conditions must
be adhered to. While powering up, V
never exceed V
25.3.4
When enabled, the on-chip regulator always consumes
a small incremental amount of current over I
includes when the device is in Sleep mode, even
though the core digital logic does not require power. To
provide additional savings in applications where power
resources are critical, the regulator can be configured
to automatically disable itself whenever the device
goes into Sleep mode. This feature is controlled by the
REGSLP bit (WDTCON<7>). Setting this bit disables
the regulator in Sleep mode, and reduces its current
consumption to a minimum.
Substantial Sleep mode power savings can be
obtained by setting the REGSLP bit, but device
wake-up time will increase in order to ensure the
regulator has enough time to stabilize.
FIGURE 25-3:
DS39933D-page 334
ON-CHIP REGULATOR AND BOR
POWER-UP REQUIREMENTS
OPERATION IN SLEEP MODE
Note 1:
CPU Clock
PLL Clock
Peripheral
Program
Counter
“Brown-out
DD
INTRC
Output
OSC1
Clock
by 0.3 volts.
T
Wake from Interrupt Event
OST
TIMING TRANSITION FOR TWO-SPEED START-UP (INTRC TO HSPLL)
= 1024 T
PC
Reset
OSC
; T
Q1
PLL
T
OST (1)
= 2 ms (approx). These intervals are not shown to scale.
(BOR)”
DDCORE
Q2
PC + 2
DD
. This
must
T
OSTS bit Set
and
Q3
PLL (1)
Q4
The REGSLP bit is automatically cleared by hardware
when a Low-Voltage Detect condition occurs. The
REGSLP bit can be set again in software, which would
continue to keep the voltage regulator in Low-Power
mode. This, however, is not recommended if any write
operations to the Flash will be performed.
25.4
The Two-Speed Start-up feature helps to minimize the
latency period, from oscillator start-up to code execu-
tion, by allowing the microcontroller to use the INTRC
oscillator as a clock source until the primary clock
source is available. It is enabled by setting the IESO
Configuration bit.
Two-Speed Start-up should be enabled only if the
Primary
(Crystal-Based) modes. Since the EC and ECPLL
modes do not require an OST start-up delay,
Two-Speed Start-up should be disabled.
When enabled, Resets and wake-ups from Sleep mode
cause the device to configure itself to run from the inter-
nal oscillator block as the clock source, following the
time-out of the Power-up Timer after a Power-on Reset
is enabled. This allows almost immediate code
execution while the primary oscillator starts and the
OST is running. Once the OST times out, the device
automatically switches to PRI_RUN mode.
In all other power-managed modes, Two-Speed
Start-up is not used. The device will be clocked by the
currently selected clock source until the primary clock
source becomes available. The setting of the IESO bit
is ignored.
Q1
1
Transition
2
Clock
Two-Speed Start-up
n-1 n
Oscillator
PC + 4
Q2
mode
 2010 Microchip Technology Inc.
Q3 Q4
is
Q1
PC + 6
Q2
HS
Q3
or
HSPLL