PIC18F67J90-I/PT Microchip Technology, PIC18F67J90-I/PT Datasheet - Page 419

• Manufacturer Part Number: PIC18F67J90-I/PT
• Description: IC PIC MCU FLASH 128KB 64-TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F67J90-I/PT

• Core Size: 8-Bit
• Program Memory Size: 128KB (64K x 16)
• Core Processor: PIC
• Speed: 48MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LCD, LVD, POR, PWM, WDT
• Number Of I /o: 51
• Program Memory Type: FLASH
• Ram Size: 3.8K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-TFQFP
• Controller Family/series: PIC18
• No. Of I/o's: 51
• Ram Memory Size: 3.8310546875KB
• Cpu Speed: 48MHz
• No. Of Timers: 4
• No. Of Pwm Channels: 2
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 3923 B
• Interface Type: AUSART, EUSART, I2C, SPI
• Maximum Clock Frequency: 48 MHz
• Number Of Programmable I/os: 51
• Number Of Timers: 4
• Operating Supply Voltage: 2.65 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 12 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC162079 - HEADER MPLAB ICD2 18F85J90 64/80AC164328 - MODULE SKT FOR 80TQFP
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

FIGURE 28-12:
TABLE 28-17: EXAMPLE SPI SLAVE MODE REQUIREMENTS (CKE = 1)
 2010 Microchip Technology Inc.
Param
70
70A
71
71A
72
72A
73A
74
75
76
77
78
79
80
82
83
Note 1:
No.
SS
SCK
(CKP = 0)
SCK
(CKP = 1)
SDO
SDI
2:
Note:
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
SS
SS
SS
SC
SC
SC
SC
SS
SC
SC
SC
SC
SS
SC
SC
Symbol
B
DO
DO
2
Requires the use of Parameter #73A.
Only if Parameter #71A and #72A are used.
L2
L2
L2
L2WB SS to write to SSPBUF
H2
H2
L2
H2
L2
H
L
H2
L2
R
F
B
R
F
DO
DO
SS
SC
SC
DI
DO
SS
Refer to Figure 28-3 for load conditions.
DI
DO
L
L,
H
V SDO Data Output Valid after SS  Edge
H,
L
V
H,
V,
Z SS  to SDO Output High-Impedance
SS  to SCK  or SCK  Input
SCK Input High Time
(Slave mode)
SCK Input Low Time
(Slave mode)
Last Clock Edge of Byte 1 to the First Clock Edge of Byte 2 1.5 T
Hold Time of SDI Data Input to SCK Edge
SDO Data Output Rise Time
SDO Data Output Fall Time
SCK Output Rise Time (Master mode)
SCK Output Fall Time (Master mode)
SDO Data Output Valid after SCK Edge
SS  after SCK Edge
82
EXAMPLE SPI SLAVE MODE TIMING (CKE = 1)
70
MSb In
MSb
74
71
75, 76
Characteristic
72
bit 6 - - - - - - 1
bit 6 - - - - 1
Continuous
Single Byte
Continuous
Single Byte
80
PIC18F87J90 FAMILY
LSb In
LSb
1.25 T
1.25 T
1.5 T
3 T
3 T
Min
CY
CY
40
40
40
—
10
—
—
—
—
—
CY
CY
CY
CY
83
+ 40
+ 40
+ 30
+ 30
77
Max Units Conditions
25
25
50
25
25
50
50
—
—
—
—
—
—
—
—
—
DS39933D-page 419
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
(Note 1)
(Note 1)
(Note 2)