PIC18F67J90-I/PT Microchip Technology, PIC18F67J90-I/PT Datasheet - Page 416

• Manufacturer Part Number: PIC18F67J90-I/PT
• Description: IC PIC MCU FLASH 128KB 64-TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F67J90-I/PT

• Core Size: 8-Bit
• Program Memory Size: 128KB (64K x 16)
• Core Processor: PIC
• Speed: 48MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LCD, LVD, POR, PWM, WDT
• Number Of I /o: 51
• Program Memory Type: FLASH
• Ram Size: 3.8K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-TFQFP
• Controller Family/series: PIC18
• No. Of I/o's: 51
• Ram Memory Size: 3.8310546875KB
• Cpu Speed: 48MHz
• No. Of Timers: 4
• No. Of Pwm Channels: 2
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 3923 B
• Interface Type: AUSART, EUSART, I2C, SPI
• Maximum Clock Frequency: 48 MHz
• Number Of Programmable I/os: 51
• Number Of Timers: 4
• Operating Supply Voltage: 2.65 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 12 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC162079 - HEADER MPLAB ICD2 18F85J90 64/80AC164328 - MODULE SKT FOR 80TQFP
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

PIC18F87J90 FAMILY
FIGURE 28-9:
TABLE 28-14: EXAMPLE SPI MODE REQUIREMENTS (MASTER MODE, CKE = 0)
DS39933D-page 416
73
73A
74
75
76
78
79
80
Note 1:
Param
No.
Note:
SCK
(CKP = 0)
SCK
(CKP = 1)
SDO
SDI
2:
T
T
T
T
T
T
T
T
T
T
T
SC
SC
SC
SC
SC
SC
DI
DI
B
DO
DO
Requires the use of Parameter #73A.
Only if Parameter #71A and #72A are used.
Symbol
2
Refer to Figure 28-3 for load conditions.
V2
V2
H2
L2
R
F
H2
L2
B
R
F
SC
SC
DI
DO
DI
DO
L
L,
H,
L
V
V,
EXAMPLE SPI MASTER MODE TIMING (CKE = 0)
Setup Time of SDI Data Input to SCK Edge
Last Clock Edge of Byte 1 to the 1st Clock Edge
of Byte 2
Hold Time of SDI Data Input to SCK Edge
SDO Data Output Rise Time
SDO Data Output Fall Time
SCK Output Rise Time (Master mode)
SCK Output Fall Time (Master mode)
SDO Data Output Valid after SCK Edge
70
80
73
MSb In
MSb
Characteristic
74
75, 76
bit 6 - - - - - - 1
bit 6 - - - - 1
78
79
1.5 T
Min
CY
20
40
79
—
—
—
—
—
78
LSb In
+ 40
 2010 Microchip Technology Inc.
Max Units
25
25
25
25
50
LSb
—
—
—
ns
ns
ns
ns
ns
ns
ns
ns
(Note 2)
Conditions