PIC18F27J53-I/SP Microchip Technology, PIC18F27J53-I/SP Datasheet - Page 9

• Manufacturer Part Number: PIC18F27J53-I/SP
• Description: IC PIC MCU 128KB FLASH 28SPDIP
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 18Fr

Specifications of PIC18F27J53-I/SP

• Program Memory Type: FLASH
• Program Memory Size: 128KB (64K x 16)
• Package / Case: *
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 48MHz
• Connectivity: I²C, LIN, SPI, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 22
• Ram Size: 3.8K x 8
• Voltage - Supply (vcc/vdd): 2.15 V ~ 3.6 V
• Data Converters: A/D 10x10b/12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 3.8 KB
• Interface Type: I2C, SPI, USART
• Maximum Clock Frequency: 48 MHz
• Number Of Programmable I/os: 16
• Number Of Timers: 8
• Operating Supply Voltage: 2.15 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: Through Hole
• Minimum Operating Temperature: - 40 C
• Controller Family/series: PIC18
• Cpu Speed: 48MHz
• Embedded Interface Type: I2C, SPI, USART
• Digital Ic Case Style: DIP
• Supply Voltage Range: 1.8V To 5.5V
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

3.0
Programming includes the ability to erase or write the
memory within the device.
The EECON1 register is used to control Write or Row
Erase operations. The WREN bit must be set to enable
writes; this must be done prior to initiating a write
sequence. It is strongly recommended that the WREN
bit only be set immediately prior to a program or erase
operation.
The FREE bit must be set in order to erase the program
space being pointed to by the Table Pointer. The erase
or write sequence is initiated by setting the WR bit.
3.1
3.1.1
Devices of the PIC18F2XJXX/4XJXX family may be
Bulk Erased by writing 0180h to the table address,
3C0005h:3C0004h. The basic sequence is shown in
Table 3-1 and demonstrated in Figure 3-1.
Since the code-protect Configuration bit is stored in the
program code within code memory, a Bulk Erase
operation will also clear any code-protect settings for
the device.
The actual Bulk Erase function is a self-timed opera-
tion. Once the erase has started (falling edge of the 4th
PGC after the NOP command), serial execution will
cease until the erase completes (parameter P11).
During this time, PGC may continue to toggle but PGD
must be held low.
FIGURE 3-2:
© 2009 Microchip Technology Inc.
PGC
PGD
4-Bit Command
DEVICE PROGRAMMING
ICSP™ Erase
1
0
ICSP™ BULK ERASE
2
0
3
1
4
1
P5
BULK ERASE TIMING
1
1
Data Payload
2
1
16-Bit
15 16
0
0
P5A
PIC18F2XJXX/4XJXX FAMILY
4-Bit Command
1
0
2
0
3
0
PGD = Input
4
0
P5
1
0
Data Payload
2
0
16-Bit
TABLE 3-1:
FIGURE 3-1:
Command
15 16
0
0000
0000
0000
0000
0000
0000
1100
0000
0000
0000
0000
0000
0000
1100
0000
0000
4-Bit
0
P5A
4-Bit Command
1
0
Payload
0E 3C
6E F8
0E 00
6E F7
0E 05
6E F6
01 01
0E 3C
6E F8
0E 00
6E F7
0E 04
6E F6
80 80
00 00
00 00
2
0
Data
BULK ERASE COMMAND
SEQUENCE
3
0
3C0004h to Erase
Delay P11 + P10
Write 8080h to
4
Entire Device
0
Write 0101h
to 3C0005h
BULK ERASE FLOW
MOVLW 3Ch
MOVWF TBLPTRU
MOVLW 00h
MOVWF TBLPTRH
MOVLW 05h
MOVWF TBLPTRL
Write 01h to 3C0005h
MOVLW 3Ch
MOVWF TBLPTRU
MOVLW 00h
MOVWF TBLPTRH
MOVLW 04h
MOVWF TBLPTRL
Write 80h TO 3C0004h to
erase entire device.
NOP
Hold PGD low until erase
completes.
Done
Time
Start
Erase Time
P11
Core Instruction
DS39687E-page 9
P10
Data Payload
16-Bit
1
n
2
n