PIC16F74-I/P Microchip Technology, PIC16F74-I/P Datasheet - Page 26

• Manufacturer Part Number: PIC16F74-I/P
• Description: IC MCU FLASH 4KX14 A/D 40DIP
• Manufacturer: Microchip Technology
• Series: PIC® 16Fr

Specifications of PIC16F74-I/P

• Core Size: 8-Bit
• Program Memory Size: 7KB (4K x 14)
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Core Processor: PIC
• Speed: 20MHz
• Connectivity: I²C, SPI, UART/USART
• Number Of I /o: 33
• Program Memory Type: FLASH
• Ram Size: 192 x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 5.5 V
• Data Converters: A/D 8x8b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 40-DIP (0.600", 15.24mm)
• Controller Family/series: PIC16F
• No. Of I/o's: 33
• Ram Memory Size: 192Byte
• Cpu Speed: 20MHz
• No. Of Timers: 3
• Package: 40PDIP
• Device Core: PIC
• Family Name: PIC16
• Maximum Speed: 20 MHz
• Operating Supply Voltage: 5 V
• Data Bus Width: 8 Bit
• Number Of Programmable I/os: 33
• Interface Type: I2C/SPI/USART
• On-chip Adc: 8-chx8-bit
• Number Of Timers: 3
• Processor Series: PIC16F
• Core: PIC
• Data Ram Size: 192 B
• Maximum Clock Frequency: 20 MHz
• Maximum Operating Temperature: + 85 C
• Mounting Style: Through Hole
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734
• Development Tools By Supplier: ICE2000, DM163022
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 444-1001 - DEMO BOARD FOR PICMICRO MCU
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

PIC16F7X
2.2.2.6
The PIE2 register contains the individual enable bits for
the CCP2 peripheral interrupt.
REGISTER 2-6:
2.2.2.7
The PIR2 register contains the flag bits for the CCP2
interrupt.
REGISTER 2-7:
DS30325B-page 24
bit 7-1
bit 0
bit 7-1
bit 0
PIE2 Register
PIR2 Register
PIE2 REGISTER (ADDRESS 8Dh)
PIR2 REGISTER (ADDRESS 0Dh)
Legend:
R = Readable bit
- n = Value at POR reset
Legend:
R = Readable bit
- n = Value at POR reset
Unimplemented: Read as '0'
CCP2IF: CCP2 Interrupt Flag bit
Capture mode:
1 = A TMR1 register capture occurred (must be cleared in software)
0 = No TMR1 register capture occurred
Compare mode:
1 = A TMR1 register compare match occurred (must be cleared in software)
0 = No TMR1 register compare match occurred
PWM mode:
Unused
bit 7
Unimplemented: Read as '0'
CCP2IE: CCP2 Interrupt Enable bit
1 = Enables the CCP2 interrupt
0 = Disables the CCP2 interrupt
bit 7
U-0
U-0
—
—
U-0
U-0
—
—
U-0
U-0
—
—
W = Writable bit
’1’ = Bit is set
W = Writable bit
’1’ = Bit is set
U-0
U-0
—
—
Note:
U = Unimplemented bit, read as ‘0’
’0’ = Bit is cleared
U = Unimplemented bit, read as ‘0’
’0’ = Bit is cleared
Interrupt flag bits are set when an interrupt
condition occurs, regardless of the state of
its corresponding enable bit or the global
enable bit, GIE (INTCON<7>). User soft-
ware should ensure the appropriate inter-
rupt flag bits are clear prior to enabling an
interrupt.
U-0
U-0
—
—
U-0
U-0
 2002 Microchip Technology Inc.
—
—
x = Bit is unknown
x = Bit is unknown
U-0
U-0
—
—
CCP2IE
CCP2IF
R/W-0
R/W-0
bit 0
bit 0