PIC16F74-I/P Microchip Technology, PIC16F74-I/P Datasheet - Page 28

• Manufacturer Part Number: PIC16F74-I/P
• Description: IC MCU FLASH 4KX14 A/D 40DIP
• Manufacturer: Microchip Technology
• Series: PIC® 16Fr

Specifications of PIC16F74-I/P

• Core Size: 8-Bit
• Program Memory Size: 7KB (4K x 14)
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Core Processor: PIC
• Speed: 20MHz
• Connectivity: I²C, SPI, UART/USART
• Number Of I /o: 33
• Program Memory Type: FLASH
• Ram Size: 192 x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 5.5 V
• Data Converters: A/D 8x8b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 40-DIP (0.600", 15.24mm)
• Controller Family/series: PIC16F
• No. Of I/o's: 33
• Ram Memory Size: 192Byte
• Cpu Speed: 20MHz
• No. Of Timers: 3
• Package: 40PDIP
• Device Core: PIC
• Family Name: PIC16
• Maximum Speed: 20 MHz
• Operating Supply Voltage: 5 V
• Data Bus Width: 8 Bit
• Number Of Programmable I/os: 33
• Interface Type: I2C/SPI/USART
• On-chip Adc: 8-chx8-bit
• Number Of Timers: 3
• Processor Series: PIC16F
• Core: PIC
• Data Ram Size: 192 B
• Maximum Clock Frequency: 20 MHz
• Maximum Operating Temperature: + 85 C
• Mounting Style: Through Hole
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734
• Development Tools By Supplier: ICE2000, DM163022
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 444-1001 - DEMO BOARD FOR PICMICRO MCU
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

PIC16F7X
2.3
The program counter (PC) is 13 bits wide. The low byte
comes from the PCL register, which is a readable and
writable register. The upper bits (PC<12:8>) are not
readable, but are indirectly writable through the
PCLATH register. On any RESET, the upper bits of the
PC will be cleared. Figure 2-4 shows the two situations
for the loading of the PC. The upper example in the fig-
ure shows how the PC is loaded on a write to PCL
(PCLATH<4:0> → PCH). The lower example in the fig-
ure shows how the PC is loaded during a CALL or GOTO
instruction (PCLATH<4:3> → PCH).
FIGURE 2-4:
2.3.1
A computed GOTO is accomplished by adding an offset
to the program counter (ADDWF PCL). When doing a
table read using a computed GOTO method, care
should be exercised if the table location crosses a PCL
memory boundary (each 256 byte block). Refer to the
Application Note, “Implementing a Table Read"
(AN556).
2.3.2
The PIC16F7X family has an 8-level deep x 13-bit wide
hardware stack. The stack space is not part of either
program or data space and the stack pointer is not
readable or writable. The PC is PUSHed onto the stack
when a CALL instruction is executed, or an interrupt
causes a branch. The stack is POPed in the event of a
RETURN, RETLW or a RETFIE instruction execution.
PCLATH is not affected by a PUSH or POP operation.
The stack operates as a circular buffer. This means that
after the stack has been PUSHed eight times, the ninth
push overwrites the value that was stored from the first
push. The tenth push overwrites the second push (and
so on).
DS30325B-page 26
PC
PC
12
12 11 10
2
PCL and PCLATH
PCH
5
PCLATH<4:3>
PCH
COMPUTED GOTO
STACK
PCLATH
PCLATH<4:0>
8
PCLATH
8
7
7
LOADING OF PC IN
DIFFERENT SITUATIONS
PCL
PCL
11
8
0
0
Instruction with
PCL as
Destination
ALU
GOTO,CALL
Opcode <10:0>
2.4
PIC16F7X devices are capable of addressing a contin-
uous 8K word block of program memory. The CALL and
GOTO instructions provide only 11 bits of address to
allow branching within any 2K program memory page.
When doing a CALL or GOTO instruction, the upper 2
bits of the address are provided by PCLATH<4:3>.
When doing a CALL or GOTO instruction, the user must
ensure that the page select bits are programmed so
that the desired program memory page is addressed. If
a return from a CALL instruction (or interrupt) is exe-
cuted, the entire 13-bit PC is popped off the stack.
Therefore, manipulation of the PCLATH<4:3> bits are
not required for the RETURN instructions (which POPs
the address from the stack).
Example 2-1 shows the calling of a subroutine in
page 1 of the program memory. This example assumes
that PCLATH is saved and restored by the Interrupt
Service Routine (if interrupts are used).
EXAMPLE 2-1:
SUB1_P1
RETURN
Note:
Note 1: There are no status bits to indicate stack
Program Memory Paging
2: There are no instructions/mnemonics
ORG
BCF
BSF
:
:
ORG
:
:
:
CALL SUB1_P1
The
unchanged after a RETURN or RETFIE
instruction is executed. The user must
setup the PCLATH for any subsequent
CALLS or GOTOS.
overflow or stack underflow conditions.
called PUSH or POP. These are actions
that occur from the execution of the
CALL, RETURN, RETLW and RETFIE
instructions, or the vectoring to an inter-
rupt address.
0x500
PCLATH,4
PCLATH,3 ;Select page 1
0x900
contents
CALL OF A SUBROUTINE
IN PAGE 1 FROM PAGE 0
 2002 Microchip Technology Inc.
;(800h-FFFh)
;Call subroutine in
;page 1 (800h-FFFh)
;page 1 (800h-FFFh)
;called subroutine
;page 1 (800h-FFFh)
;return to Call
;subroutine in page 0
;(000h-7FFh)
of
the
PCLATH
are