PIC18F2455-I/SP Microchip Technology, PIC18F2455-I/SP Datasheet - Page 9

• Manufacturer Part Number: PIC18F2455-I/SP
• Description: IC PIC MCU FLASH 12KX16 28DIP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F2455-I/SP

• Program Memory Type: FLASH
• Program Memory Size: 24KB (12K x 16)
• Package / Case: 28-DIP (0.300", 7.62mm)
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 48MHz
• Connectivity: I²C, SPI, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, HLVD, POR, PWM, WDT
• Number Of I /o: 24
• Eeprom Size: 256 x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 10x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 2 KB
• Interface Type: SPI/I2C/EAUSART
• Maximum Clock Frequency: 48 MHz
• Number Of Programmable I/os: 24
• Number Of Timers: 4
• Operating Supply Voltage: 2 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: Through Hole
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, ICE4000, DM163014, DV164136
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10-ch x 10-bit
• Package: 28SPDIP
• Device Core: PIC
• Family Name: PIC18
• Maximum Speed: 48 MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: I3-DB18F4550 - BOARD DAUGHTER ICEPIC3DM163025 - PIC DEM FULL SPEED USB DEMO BRDDVA18XP280 - DEVICE ADAPTER 18F2220 PDIP 28LD
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

11. Module: PORTD
12. Module: MSSP
13. Module: EUSART
bit 4 SCKP: Synchronous Clock Polarity Select bit
© 2009 Microchip Technology Inc.
Each of the PORTD pins has a weak internal pull-up.
A single control bit, RDPU (PORTE<7>), can turn on
all the pull-ups. After the pull-up has been enabled
(PORTE<7> = 1), any access to the PORTE register
would cause the RDPU control bit to clear, except
those accesses that write a '1' to PORTE<7>.
Work around
Reassert RDPU after every access to the PORTE
register, except those accesses that write a ‘1’ to
PORTE<7> or use external pull-ups.
Affected Silicon Revisions
The I
supported. Therefore, SSPCON2 register bits,
ADMSK<5:1>, do not exist in I
Work around
None.
Affected Silicon Revisions
In the BAUDCON register, bits, RXDTP and TXCKP,
do not exist. BAUDCON bit 4 is defined instead as
SCKP and has the following definition:
Work around
None.
Affected Silicon Revisions
Asynchronous mode:
Unused in this mode.
Synchronous mode:
1 = Idle state for clock (CK) is a high level
0 = Idle state for clock (CK) is a low level
A3
A3
A3
X
X
X
2
C™ slave address masking feature is not
B4
B4
B4
B5
B5
B5
2
C Slave mode.
B6
B6
B6
PIC18F2455/2550/4455/4550
B7
B7
B7
14. Module: USB
15. Module: MSSP
16. Module: MSSP
The Ping-Pong Buffer mode in which the ping-pong
buffers are enabled for Endpoints 1 to 15 (UCFG
(PPB<1:0) = 11) is not supported.
Work around
Use other Ping-Pong Buffer modes.
Affected Silicon Revisions
The MSSP configured in SPI Slave mode will
generate a write collision if SSPBUF is updated and
the previous SSPBUF contents have not been
transferred
Re-initializing the MSSP by clearing and setting the
SSPEN bit (SSPCON1<5>), prior to rewriting
SSPBUF, will not prevent the error condition.
Work around
Prior to updating the SSPBUF register with a new
value, verify whether the previous contents were
transferred by reading the BF bit (SSPSTAT<0>). If
the previous byte has not been transferred, update
SSPBUF and clear the WCOL bit (SSPCON1<7>) if
necessary.
Affected Silicon Revisions
In SPI mode, the SDO output may change after the
inactive clock edge of the bit ‘0’ output. This may
affect some SPI components that read data over
300 ns after the inactive edge of SCK.
Work around
None.
Affected Silicon Revisions
A3
A3
A3
X
X
X
to the shift register
B4
B4
B4
B5
B5
B5
.
DS80478A-page 9
B6
B6
B6
B7
B7
B7