PIC16LF873A-I/ML Microchip Technology, PIC16LF873A-I/ML Datasheet - Page 25

• Manufacturer Part Number: PIC16LF873A-I/ML
• Description: IC PIC MCU FLASH 4KX14 28QFN
• Manufacturer: Microchip Technology
• Series: PIC® 16Fr

Specifications of PIC16LF873A-I/ML

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 10MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 22
• Program Memory Size: 7KB (4K x 14)
• Program Memory Type: FLASH
• Eeprom Size: 128 x 8
• Ram Size: 192 x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 5.5 V
• Data Converters: A/D 5x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-VQFN Exposed Pad, 28-HVQFN, 28-SQFN, 28-DHVQFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: PIC16LF873A-I/MLR; PIC16LF873A-I/MLR

2.2.2.2
The OPTION_REG Register is a readable and writable
register, which contains various control bits to configure
the TMR0 prescaler/WDT postscaler (single assign-
able register known also as the prescaler), the external
INT interrupt, TMR0 and the weak pull-ups on PORTB.
REGISTER 2-2:
 2003 Microchip Technology Inc.
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2-0
OPTION_REG Register
OPTION_REG REGISTER (ADDRESS 81h, 181h)
Bit Value TMR0 Rate WDT Rate
bit 7
RBPU: PORTB Pull-up Enable bit
1 = PORTB pull-ups are disabled
0 = PORTB pull-ups are enabled by individual port latch values
INTEDG: Interrupt Edge Select bit
1 = Interrupt on rising edge of RB0/INT pin
0 = Interrupt on falling edge of RB0/INT pin
T0CS: TMR0 Clock Source Select bit
1 = Transition on RA4/T0CKI pin
0 = Internal instruction cycle clock (CLKO)
T0SE: TMR0 Source Edge Select bit
1 = Increment on high-to-low transition on RA4/T0CKI pin
0 = Increment on low-to-high transition on RA4/T0CKI pin
PSA: Prescaler Assignment bit
1 = Prescaler is assigned to the WDT
0 = Prescaler is assigned to the Timer0 module
PS2:PS0: Prescaler Rate Select bits
Legend:
R = Readable bit
- n = Value at POR
Note:
R/W-1
RBPU
000
001
010
011
100
101
110
111
When using Low-Voltage ICSP Programming (LVP) and the pull-ups on PORTB are
enabled, bit 3 in the TRISB register must be cleared to disable the pull-up on RB3
and ensure the proper operation of the device
INTEDG
R/W-1
1 : 2
1 : 4
1 : 8
1 : 16
1 : 32
1 : 64
1 : 128
1 : 256
R/W-1
T0CS
1 : 1
1 : 2
1 : 4
1 : 8
1 : 16
1 : 32
1 : 64
1 : 128
W = Writable bit
‘1’ = Bit is set
R/W-1
T0SE
Note:
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
R/W-1
PSA
To achieve a 1:1 prescaler assignment for
the TMR0 register, assign the prescaler to
the Watchdog Timer.
PIC16F87XA
R/W-1
PS2
x = Bit is unknown
R/W-1
PS1
DS39582B-page 23
R/W-1
PS0
bit 0