PIC16LF873A-I/ML Microchip Technology, PIC16LF873A-I/ML Datasheet - Page 68

• Manufacturer Part Number: PIC16LF873A-I/ML
• Description: IC PIC MCU FLASH 4KX14 28QFN
• Manufacturer: Microchip Technology
• Series: PIC® 16Fr

Specifications of PIC16LF873A-I/ML

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 10MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 22
• Program Memory Size: 7KB (4K x 14)
• Program Memory Type: FLASH
• Eeprom Size: 128 x 8
• Ram Size: 192 x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 5.5 V
• Data Converters: A/D 5x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-VQFN Exposed Pad, 28-HVQFN, 28-SQFN, 28-DHVQFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: PIC16LF873A-I/MLR; PIC16LF873A-I/MLR

PIC16F87XA
8.2
In Compare mode, the 16-bit CCPR1 register value is
constantly compared against the TMR1 register pair
value. When a match occurs, the RC2/CCP1 pin is:
• Driven high
• Driven low
• Remains unchanged
The action on the pin is based on the value of control
bits, CCP1M3:CCP1M0 (CCP1CON<3:0>). At the
same time, interrupt flag bit CCP1IF is set.
FIGURE 8-2:
8.2.1
The user must configure the RC2/CCP1 pin as an
output by clearing the TRISC<2> bit.
DS39582B-page 66
RC2/CCP1
Note:
Special event trigger will:
pin
Output Enable
reset Timer1, but not set interrupt flag bit TMR1IF (PIR1<0>)
and set bit GO/DONE (ADCON0<2>).
TRISC<2>
Compare Mode
CCP PIN CONFIGURATION
Clearing the CCP1CON register will force
the RC2/CCP1 compare output latch to
the default low level. This is not the
PORTC I/O data latch.
Q
Special Event Trigger
R
S
CCP1CON<3:0>
Mode Select
Output
Logic
COMPARE MODE
OPERATION BLOCK
DIAGRAM
(PIR1<2>)
Set Flag bit CCP1IF
Match
CCPR1H CCPR1L
TMR1H
Comparator
TMR1L
8.2.2
Timer1 must be running in Timer mode, or Synchro-
nized Counter mode, if the CCP module is using the
compare feature. In Asynchronous Counter mode, the
compare operation may not work.
8.2.3
When Generate Software Interrupt mode is chosen, the
CCP1 pin is not affected. The CCPIF bit is set, causing
a CCP interrupt (if enabled).
8.2.4
In this mode, an internal hardware trigger is generated
which may be used to initiate an action.
The special event trigger output of CCP1 resets the
TMR1 register pair. This allows the CCPR1 register to
effectively be a 16-bit programmable period register for
Timer1.
The special event trigger output of CCP2 resets the
TMR1 register pair and starts an A/D conversion (if the
A/D module is enabled).
Note:
TIMER1 MODE SELECTION
SOFTWARE INTERRUPT MODE
SPECIAL EVENT TRIGGER
The special event trigger from the CCP1
and CCP2 modules will not set interrupt
flag bit TMR1IF (PIR1<0>).
 2003 Microchip Technology Inc.