PIC16LF873A-I/ML Microchip Technology, PIC16LF873A-I/ML Datasheet - Page 82

• Manufacturer Part Number: PIC16LF873A-I/ML
• Description: IC PIC MCU FLASH 4KX14 28QFN
• Manufacturer: Microchip Technology
• Series: PIC® 16Fr

Specifications of PIC16LF873A-I/ML

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 10MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 22
• Program Memory Size: 7KB (4K x 14)
• Program Memory Type: FLASH
• Eeprom Size: 128 x 8
• Ram Size: 192 x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 5.5 V
• Data Converters: A/D 5x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-VQFN Exposed Pad, 28-HVQFN, 28-SQFN, 28-DHVQFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: PIC16LF873A-I/MLR; PIC16LF873A-I/MLR

PIC16F87XA
9.4
The MSSP module in I
master and slave functions (including general call sup-
port) and provides interrupts on Start and Stop bits in
hardware to determine a free bus (multi-master func-
tion). The MSSP module implements the standard
mode specifications, as well as 7-bit and 10-bit
addressing.
Two pins are used for data transfer:
• Serial clock (SCL) – RC3/SCK/SCL
• Serial data (SDA) – RC4/SDI/SDA
The user must configure these pins as inputs or outputs
through the TRISC<4:3> bits.
FIGURE 9-7:
DS39582B-page 80
RC3/SCK/SCL
RC4/SDI/
SDA
I
2
C Mode
Shift
Clock
Read
MSb
MSSP BLOCK DIAGRAM
(I
2
2
Stop bit Detect
SSPBUF reg
Match Detect
C mode fully implements all
C MODE)
SSPADD reg
SSPSR reg
Start and
LSb
Write
Internal
Data Bus
(SSPSTAT reg)
Addr Match
Set, Reset
S, P bits
9.4.1
The MSSP module has six registers for I
These are:
• MSSP Control Register (SSPCON)
• MSSP Control Register 2 (SSPCON2)
• MSSP Status Register (SSPSTAT)
• Serial Receive/Transmit Buffer Register
• MSSP Shift Register (SSPSR) – Not directly
• MSSP Address Register (SSPADD)
SSPCON, SSPCON2 and SSPSTAT are the control
and status registers in I
SSPCON and SSPCON2 registers are readable and
writable. The lower six bits of the SSPSTAT are
read-only. The upper two bits of the SSPSTAT are
read/write.
SSPSR is the shift register used for shifting data in or
out. SSPBUF is the buffer register to which data bytes
are written to or read from.
SSPADD register holds the slave device address
when the SSP is configured in I
the SSP is configured in Master mode, the lower
seven bits of SSPADD act as the baud rate generator
reload value.
In receive operations, SSPSR and SSPBUF together
create a double-buffered receiver. When SSPSR
receives a complete byte, it is transferred to SSPBUF
and the SSPIF interrupt is set.
During transmission, the SSPBUF is not double-
buffered. A write to SSPBUF will write to both SSPBUF
and SSPSR.
(SSPBUF)
accessible
REGISTERS
 2003 Microchip Technology Inc.
2
C mode operation. The
2
C Slave mode. When
2
C operation.