PIC16LF873A-I/ML Microchip Technology, PIC16LF873A-I/ML Datasheet - Page 48

• Manufacturer Part Number: PIC16LF873A-I/ML
• Description: IC PIC MCU FLASH 4KX14 28QFN
• Manufacturer: Microchip Technology
• Series: PIC® 16Fr

Specifications of PIC16LF873A-I/ML

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 10MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 22
• Program Memory Size: 7KB (4K x 14)
• Program Memory Type: FLASH
• Eeprom Size: 128 x 8
• Ram Size: 192 x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 5.5 V
• Data Converters: A/D 5x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-VQFN Exposed Pad, 28-HVQFN, 28-SQFN, 28-DHVQFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: PIC16LF873A-I/MLR; PIC16LF873A-I/MLR

PIC16F87XA
4.3
PORTC is an 8-bit wide, bidirectional port. The corre-
sponding data direction register is TRISC. Setting a
TRISC bit (= 1) will make the corresponding PORTC
pin an input (i.e., put the corresponding output driver in
a High-Impedance mode). Clearing a TRISC bit (= 0)
will make the corresponding PORTC pin an output (i.e.,
put the contents of the output latch on the selected pin).
PORTC is multiplexed with several peripheral functions
(Table 4-5). PORTC pins have Schmitt Trigger input
buffers.
When the I
pins can be configured with normal I
SMBus levels, by using the CKE bit (SSPSTAT<6>).
When enabling peripheral functions, care should be
taken in defining TRIS bits for each PORTC pin. Some
peripherals override the TRIS bit to make a pin an
output, while other peripherals override the TRIS bit to
make a pin an input. Since the TRIS bit override is in
effect while the peripheral is enabled, read-modify-
write instructions (BSF, BCF, XORWF) with TRISC as the
destination, should be avoided. The user should refer
to the corresponding peripheral section for the correct
TRIS bit settings.
FIGURE 4-6:
DS39582B-page 46
Note 1: I/O pins have diode protection to V
Port/Peripheral Select
Peripheral Data Out
Data Bus
WR Port
WR TRIS
RD TRIS
Peripheral
OE
RD Port
Peripheral Input
(3)
2: Port/Peripheral Select signal selects between port
3: Peripheral OE (Output Enable) is only activated if
PORTC and the TRISC Register
data and peripheral output.
Peripheral Select is active.
2
C module is enabled, the PORTC<4:3>
TRIS Latch
Data Latch
D
D
CK
CK
Q
Q
Q
Q
(2)
PORTC BLOCK DIAGRAM
(PERIPHERAL OUTPUT
OVERRIDE) RC<2:0>,
RC<7:5>
0
1
Q
EN
D
2
DD
Schmitt
Trigger
C levels, or with
and V
V
V
N
P
SS
DD
SS
.
pin
I/O
(1)
FIGURE 4-7:
Port/Peripheral Select
Peripheral Data Out
Data Bus
WR Port
WR TRIS
RD TRIS
Peripheral
OE
RD Port
SSP Input
Note 1: I/O pins have diode protection to V
(3)
2: Port/Peripheral Select signal selects between port data
3: Peripheral OE (Output Enable) is only activated if
and peripheral output.
Peripheral Select is active.
TRIS Latch
Data Latch
D
D
CK
CK
Q
Q
Q
Q
(2)
PORTC BLOCK DIAGRAM
(PERIPHERAL OUTPUT
OVERRIDE) RC<4:3>
 2003 Microchip Technology Inc.
0
1
Q
CKE
SSPSTAT<6>
EN
D
Schmitt
Trigger
DD
and V
V
0
1
V
N
P
SS
DD
SS
Schmitt
Trigger
with
SMBus
Levels
.
pin
I/O
(1)