PIC18F4585-I/PT Microchip Technology, PIC18F4585-I/PT Datasheet - Page 191

• Manufacturer Part Number: PIC18F4585-I/PT
• Description: IC MCU FLASH 24KX16 44TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F4585-I/PT

• Core Size: 8-Bit
• Program Memory Size: 48KB (24K x 16)
• Core Processor: PIC
• Speed: 40MHz
• Connectivity: CAN, I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, HLVD, POR, PWM, WDT
• Number Of I /o: 36
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 3.25K x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 11x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-TQFP, 44-VQFP
• Controller Family/series: PIC18
• No. Of I/o's: 36
• Eeprom Memory Size: 1024Byte
• Ram Memory Size: 3.25KB
• Cpu Speed: 40MHz
• No. Of Timers: 4
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: XLT44PT3 - SOCKET TRAN ICE 44MQFP/TQFPI3-DB18F4680 - BOARD DAUGHTER ICEPIC3AC164305 - MODULE SKT FOR PM3 44TQFP444-1001 - DEMO BOARD FOR PICMICRO MCUAC164020 - MODULE SKT PROMATEII 44TQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

REGISTER 17-2:
© 2007 Microchip Technology Inc.
bit 7
bit 6
bit 5
bit 4
bit 3-0 SSPM3:SSPM0: Synchronous Serial Port Mode Select bits
SSPCON1: MSSP CONTROL REGISTER 1 (SPI MODE)
bit 7
WCOL: Write Collision Detect bit (Transmit mode only)
1 = The SSPBUF register is written while it is still transmitting the previous word
0 = No collision
SSPOV: Receive Overflow Indicator bit
SPI Slave mode:
1 = A new byte is received while the SSPBUF register is still holding the previous data. In case
0 = No overflow
SSPEN: Synchronous Serial Port Enable bit
1 = Enables serial port and configures SCK, SDO, SDI and SS as serial port pins
0 = Disables serial port and configures these pins as I/O port pins
CKP: Clock Polarity Select bit
1 = Idle state for clock is a high level
0 = Idle state for clock is a low level
0101 = SPI Slave mode, clock = SCK pin, SS pin control disabled, SS can be used as I/O pin
0100 = SPI Slave mode, clock = SCK pin, SS pin control enabled
0011 = SPI Master mode, clock = TMR2 output/2
0010 = SPI Master mode, clock = F
0001 = SPI Master mode, clock = F
0000 = SPI Master mode, clock = F
Legend:
R = Readable bit
-n = Value at POR
WCOL
R/W-0
Note:
Note:
Note:
(must be cleared in software)
of overflow, the data in SSPSR is lost. Overflow can only occur in Slave mode. The user
must read the SSPBUF, even if only transmitting data, to avoid setting overflow (must be
cleared in software).
In Master mode, the overflow bit is not set since each new reception (and
transmission) is initiated by writing to the SSPBUF register.
When enabled, these pins must be properly configured as input or output.
Bit combinations not specifically listed here are either reserved or implemented in
I
2
SSPOV
C mode only.
R/W-0
PIC18F2585/2680/4585/4680
W = Writable bit
‘1’ = Bit is set
SSPEN
R/W-0
Preliminary
OSC
OSC
OSC
R/W-0
CKP
/64
/16
/4
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
SSPM3
R/W-0
SSPM2
R/W-0
x = Bit is unknown
SSPM1
R/W-0
DS39625C-page 189
SSPM0
R/W-0
bit 0