PIC18F4585-I/PT Microchip Technology, PIC18F4585-I/PT Datasheet - Page 199

IC MCU FLASH 24KX16 44TQFP

PIC18F4585-I/PT

Manufacturer Part Number
PIC18F4585-I/PT
Description
IC MCU FLASH 24KX16 44TQFP
Manufacturer
Microchip Technology
Series
PIC® 18Fr

Specifications of PIC18F4585-I/PT

Core Size
8-Bit
Program Memory Size
48KB (24K x 16)
Core Processor
PIC
Speed
40MHz
Connectivity
CAN, I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, HLVD, POR, PWM, WDT
Number Of I /o
36
Program Memory Type
FLASH
Eeprom Size
1K x 8
Ram Size
3.25K x 8
Voltage - Supply (vcc/vdd)
4.2 V ~ 5.5 V
Data Converters
A/D 11x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
44-TQFP, 44-VQFP
Controller Family/series
PIC18
No. Of I/o's
36
Eeprom Memory Size
1024Byte
Ram Memory Size
3.25KB
Cpu Speed
40MHz
No. Of Timers
4
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
XLT44PT3 - SOCKET TRAN ICE 44MQFP/TQFPI3-DB18F4680 - BOARD DAUGHTER ICEPIC3AC164305 - MODULE SKT FOR PM3 44TQFP444-1001 - DEMO BOARD FOR PICMICRO MCUAC164020 - MODULE SKT PROMATEII 44TQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
PIC18F4585-I/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
Part Number:
PIC18F4585-I/PT
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
REGISTER 17-3:
© 2007 Microchip Technology Inc.
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
bit 7
SMP: Slew Rate Control bit
In Master or Slave mode:
1 = Slew rate control disabled for Standard Speed mode (100 kHz and 1 MHz)
0 = Slew rate control enabled for High-Speed mode (400 kHz)
CKE: SMBus Select bit
In Master or Slave mode:
1 = Enable SMBus specific inputs
0 = Disable SMBus specific inputs
D/A: Data/Address bit
In Master mode:
Reserved.
In Slave mode:
1 = Indicates that the last byte received or transmitted was data
0 = Indicates that the last byte received or transmitted was address
P: Stop bit
1 = Indicates that a Stop bit has been detected last
0 = Stop bit was not detected last
S: Start bit
1 = Indicates that a Start bit has been detected last
0 = Start bit was not detected last
R/W: Read/Write bit Information (I
In Slave mode:
1 = Read
0 = Write
In Master mode:
1 = Transmit is in progress
0 = Transmit is not in progress
UA: Update Address bit (10-bit Slave mode only)
1 = Indicates that the user needs to update the address in the SSPADD register
0 = Address does not need to be updated
BF: Buffer Full Status bit
In Receive mode:
1 = Receive complete, SSPBUF is full
0 = Receive not complete, SSPBUF is empty
In Transmit mode:
1 = Data transmit in progress (does not include the ACK and Stop bits), SSPBUF is full
0 = Data transmit complete (does not include the ACK and Stop bits), SSPBUF is empty
Legend:
R = Readable bit
-n = Value at POR
SSPSTAT: MSSP STATUS REGISTER (I
R/W-0
Note 1: This bit is cleared on Reset and when SSPEN is cleared.
SMP
2: This bit holds the R/W bit information following the last address match. This bit is only
3: ORing this bit with SEN, RSEN, PEN, RCEN or ACKEN will indicate if the MSSP is
(1)
(1)
valid from the address match to the next Start bit, Stop bit or not ACK bit.
in Idle mode.
R/W-0
CKE
PIC18F2585/2680/4585/4680
W = Writable bit
‘1’ = Bit is set
R-0
D/A
Preliminary
2
C mode only)
R-0
P
(1)
2
C MODE)
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
(2,3)
R-0
S
(1)
R/W
R-0
(2,3)
x = Bit is unknown
R-0
UA
DS39625C-page 197
R-0
BF
bit 0

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