PIC18F4585-I/PT Microchip Technology, PIC18F4585-I/PT Datasheet - Page 360

IC MCU FLASH 24KX16 44TQFP

PIC18F4585-I/PT

Manufacturer Part Number
PIC18F4585-I/PT
Description
IC MCU FLASH 24KX16 44TQFP
Manufacturer
Microchip Technology
Series
PIC® 18Fr

Specifications of PIC18F4585-I/PT

Core Size
8-Bit
Program Memory Size
48KB (24K x 16)
Core Processor
PIC
Speed
40MHz
Connectivity
CAN, I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, HLVD, POR, PWM, WDT
Number Of I /o
36
Program Memory Type
FLASH
Eeprom Size
1K x 8
Ram Size
3.25K x 8
Voltage - Supply (vcc/vdd)
4.2 V ~ 5.5 V
Data Converters
A/D 11x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
44-TQFP, 44-VQFP
Controller Family/series
PIC18
No. Of I/o's
36
Eeprom Memory Size
1024Byte
Ram Memory Size
3.25KB
Cpu Speed
40MHz
No. Of Timers
4
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
XLT44PT3 - SOCKET TRAN ICE 44MQFP/TQFPI3-DB18F4680 - BOARD DAUGHTER ICEPIC3AC164305 - MODULE SKT FOR PM3 44TQFP444-1001 - DEMO BOARD FOR PICMICRO MCUAC164020 - MODULE SKT PROMATEII 44TQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
PIC18F4585-I/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
Part Number:
PIC18F4585-I/PT
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
PIC18F2585/2680/4585/4680
24.5.1
The program memory may be read to or written from
any location using the table read and table write
instructions. The device ID may be read with table
reads. The Configuration registers may be read and
written with the table read and table write instructions.
In normal execution mode, the CPn bits have no direct
effect. CPn bits inhibit external reads and writes. A
block of user memory may be protected from table
writes if the WRTn Configuration bit is ‘0’. The EBTRn
bits control table reads. For a block of user memory
with the EBTRn bit set to ‘0’, a table read instruction
that executes from within that block is allowed to read.
FIGURE 24-6:
DS39625C-page 358
Results: All table writes disabled to Blockn whenever WRTn = 0.
TBLPTR = 0008FFh
Register Values
PC = 00BFFEh
PC = 003FFEh
PROGRAM MEMORY
CODE PROTECTION
TABLE WRITE (WRTn) DISALLOWED
Program Memory
Preliminary
TBLWT*
TBLWT*
A table read instruction that executes from a location
outside of that block is not allowed to read and will
result in reading ‘0’s. Figures 24-6 through 24-8
illustrate table write and table read protection.
Note:
000000h
0007FFh
000800h
003FFFh
004000h
007FFFh
008000h
00BFFFh
00C000h
00FFFFh
Code protection bits may only be written to
a ‘0’ from a ‘1’ state. It is not possible to
write a ‘1’ to a bit in the ‘0’ state. Code
protection bits are only set to ‘1’ by a full
chip erase or block erase function. The full
chip erase and block erase functions can
only be initiated via ICSP or an external
programmer.
Configuration Bit Settings
WRTB, EBTRB = 11
© 2007 Microchip Technology Inc.
WRT0, EBTR0 = 01
WRT1, EBTR1 = 11
WRT2, EBTR2 = 11
WRT3, EBTR3 = 11

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