ATMEGA406-1AAU Atmel, ATMEGA406-1AAU Datasheet - Page 128

• Manufacturer Part Number: ATMEGA406-1AAU
• Description: IC AVR MCU 40K 1MHZ 48LQFP
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA406-1AAU

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 1MHz
• Connectivity: I²C
• Peripherals: POR, WDT
• Number Of I /o: 18
• Program Memory Size: 40KB (20K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 512 x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 25 V
• Data Converters: A/D 10x12b
• Oscillator Type: Internal
• Operating Temperature: -30°C ~ 85°C
• Package / Case: 48-LQFP
• Processor Series: ATMEGA48x
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 2 KB
• Interface Type: 2-Wire
• Maximum Clock Frequency: 1 MHz
• Number Of Programmable I/os: 18
• Number Of Timers: 2
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT
• Minimum Operating Temperature: - 30 C
• Cpu Family: ATmega
• Device Core: AVR
• Device Core Size: 8b
• Frequency (max): 1MHz
• Total Internal Ram Size: 2KB
• # I/os (max): 18
• Number Of Timers - General Purpose: 2
• Operating Supply Voltage (typ): 5/9/12/15/18/24V
• Operating Supply Voltage (max): 25V
• Operating Supply Voltage (min): 4V
• On-chip Adc: 10-chx12-bit
• Instruction Set Architecture: RISC
• Operating Temp Range: -30C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 48
• Package Type: LQFP
• Controller Family/series: AVR MEGA
• No. Of I/o's: 18
• Eeprom Memory Size: 512Byte
• Ram Memory Size: 2KB
• Cpu Speed: 1MHz
• Rohs Compliant: Yes
• For Use With: 770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAG770-1005 - ISP 4PORT FOR ATMEL AVR MCU JTAG770-1004 - ISP 4PORT FOR ATMEL AVR MCU SPI
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

22.7
22.7.1
22.7.2
128
Register Description for Battery Protection
ATmega406
BPPLR – Battery Protection Parameter Lock Register
BPCR – Battery Protection Control Register
to detect that it came from a Power-off situation by monitoring CPU reset flags when it resumes
operation.
The Battery Protection module operates in a different clock domain than the CPU. Whenever a
new value is written to BPCR, BPDUV, BPOCD, BPSCD, or CPBTR, the value must be synchro-
nized to the Battery Protection clock domain. Subsequent writes to this register should not be
made during this synchronization. Therefore, after writing to one of these registers, the same
register should not be re-written within the next 8 CPU clock periods. Note that each register is
synchronized independently of the others.
• Bit 7:2 – Res: Reserved Bits
These bits are reserved bits in the ATmega406 and will always read as zero.
• Bit 1 – BPPLE: Battery Protection Parameter Lock Enable
• Bit 0 – BPPL: Battery Protection Parameter Lock
The Battery Protection parameters set in the Battery Protection Parameter Registers and the
disable function set in the Battery Protection Disable Register can be locked from any further
software updates. Once locked, these registers cannot be accessed until the next hardware
reset. This provides a safe method for protecting these registers from unintentional modification
by software runaway. It is recommended that software sets these registers shortly after reset,
and then protects these registers from any further updates.
To lock these registers, the following algorithm must be followed:
1. In the same operation, write a logic one to BPPLE and BPPL.
2. Within the next four clock cycles, in the same operation. write a logic zero to BPPLE and
The Battery Protection Parameter Registers are BPCR, CBPTR, BPOCP, BPSCD and BPDUV.
• Bit 7:4 – Res: Reserved Bits
These bits are reserved bits in the ATmega406 and will always read as zero.
• Bit 3 – DUVD: Deep Under-voltage Protection Disable
Bit
(0xF8)
Read/Write
Initial Value
Bit
(0xF7)
Read/Write
Initial Value
a logic one to BPPL.
R
R
7
–
0
7
–
0
R
R
6
–
0
6
–
0
R
R
5
–
0
5
–
0
R
R
4
–
0
4
–
0
DUVD
R/W
R
3
–
0
3
0
SCD
R/W
R
2
–
0
2
0
BPPLE
DCD
R/W
R/W
1
0
1
0
BPPL
CCD
R/W
R/W
0
0
0
0
2548E–AVR–07/06
BPPLR
BPCR