DSPIC30F6013A-30I/PF Microchip Technology, DSPIC30F6013A-30I/PF Datasheet - Page 20

• Manufacturer Part Number: DSPIC30F6013A-30I/PF
• Description: IC DSPIC MCU/DSP 132K 80TQFP
• Manufacturer: Microchip Technology
• Series: dsPIC™ 30Fr

Specifications of DSPIC30F6013A-30I/PF

• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 30 MIPs
• Connectivity: CAN, I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 68
• Program Memory Size: 132KB (44K x 24)
• Program Memory Type: FLASH
• Eeprom Size: 2K x 8
• Ram Size: 6K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 5.5 V
• Data Converters: A/D 16x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-TQFP, 80-VQFP
• Core Frequency: 40MHz
• Core Supply Voltage: 5.5V
• Embedded Interface Type: CAN, I2C, SPI, UART
• No. Of I/o's: 68
• Flash Memory Size: 132KB
• Supply Voltage Range: 2.5V To 5.5V
• Package: 80TQFP
• Device Core: dsPIC
• Family Name: dsPIC30
• Maximum Speed: 30 MHz
• Operating Supply Voltage: 3.3|5 V
• Data Bus Width: 16 Bit
• Number Of Programmable I/os: 68
• Interface Type: CAN/I2C/SPI/UART
• On-chip Adc: 16-chx12-bit
• Number Of Timers: 5
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: DM300024 - KIT DEMO DSPICDEM 1.1AC164314 - MODULE SKT FOR PM3 80PFAC30F001 - MODULE SOCKET DSPIC30F 80TQFPXLT80PT2 - SOCKET TRANSITION ICE 80TQFPDV164005 - KIT ICD2 SIMPLE SUIT W/USB CABLE
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

dsPIC30F6011A/6012A/6013A/6014A
2.3
The dsPIC DSC devices feature a 16/16-bit signed
fractional divide operation, as well as 32/16-bit and
16/16-bit
operations, in the form of single instruction iterative
divides. The
following instructions and data sizes are supported:
• DIVF - 16/16 signed fractional divide
• DIV.sd - 32/16 signed divide
• DIV.ud - 32/16 unsigned divide
• DIV.sw - 16/16 signed divide
• DIV.uw - 16/16 unsigned divide
The 16/16 divides are similar to the 32/16 (same number
of iterations), but the dividend is either zero-extended or
sign-extended during the first iteration.
TABLE 2-1:
DS70143D-page 20
DIVF
DIV.sd
DIV.ud
DIV.sw
DIV.uw
Instruction
Divide Support
signed
DIVIDE INSTRUCTIONS
and
Signed fractional divide: Wm/Wn → W0; Rem → W1
Signed divide: (Wm + 1:Wm)/Wn → W0; Rem → W1
Unsigned divide: (Wm + 1:Wm)/Wn → W0; Rem → W1
Signed divide: Wm/Wn → W0; Rem → W1
Unsigned divide: Wm/Wn → W0; Rem → W1
unsigned
integer
divide
The divide instructions must be executed within a
REPEAT loop. Any other form of execution (e.g., a
series of discrete divide instructions) will not function
correctly because the instruction flow depends on
RCOUNT. The divide instruction does not automatically
set up the RCOUNT value and it must, therefore, be
explicitly and correctly specified in the REPEAT
instruction as shown in Table 2-1 (REPEAT will execute
the target instruction {operand value + 1} times). The
REPEAT loop count must be setup for 18 iterations of
the DIV/DIVF instruction. Thus, a complete divide
operation requires 19 cycles.
Function
Note:
The divide flow is interruptible. However,
the user needs to save the context as
appropriate.
© 2008 Microchip Technology Inc.