DSPIC30F6013A-30I/PF Microchip Technology, DSPIC30F6013A-30I/PF Datasheet - Page 228

• Manufacturer Part Number: DSPIC30F6013A-30I/PF
• Description: IC DSPIC MCU/DSP 132K 80TQFP
• Manufacturer: Microchip Technology
• Series: dsPIC™ 30Fr

Specifications of DSPIC30F6013A-30I/PF

• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 30 MIPs
• Connectivity: CAN, I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 68
• Program Memory Size: 132KB (44K x 24)
• Program Memory Type: FLASH
• Eeprom Size: 2K x 8
• Ram Size: 6K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 5.5 V
• Data Converters: A/D 16x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-TQFP, 80-VQFP
• Core Frequency: 40MHz
• Core Supply Voltage: 5.5V
• Embedded Interface Type: CAN, I2C, SPI, UART
• No. Of I/o's: 68
• Flash Memory Size: 132KB
• Supply Voltage Range: 2.5V To 5.5V
• Package: 80TQFP
• Device Core: dsPIC
• Family Name: dsPIC30
• Maximum Speed: 30 MHz
• Operating Supply Voltage: 3.3|5 V
• Data Bus Width: 16 Bit
• Number Of Programmable I/os: 68
• Interface Type: CAN/I2C/SPI/UART
• On-chip Adc: 16-chx12-bit
• Number Of Timers: 5
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: DM300024 - KIT DEMO DSPICDEM 1.1AC164314 - MODULE SKT FOR PM3 80PFAC30F001 - MODULE SOCKET DSPIC30F 80TQFPXLT80PT2 - SOCKET TRANSITION ICE 80TQFPDV164005 - KIT ICD2 SIMPLE SUIT W/USB CABLE
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

dsPIC30F6011A/6012A/6013A/6014A
Data Converter Interface (DCI) Module ............................ 125
Data EEPROM Memory ...................................................... 65
DC Characteristics ............................................................ 177
DCI Module
DS70143D-page 228
Alignment .................................................................... 36
Alignment (Figure) ...................................................... 37
Effect of Invalid Memory Accesses (Table)................. 36
MCU and DSP (MAC Class) Instructions Example..... 36
Memory Map ............................................................... 33
Memory Map for dsPIC30F6011A/6013A ................... 34
Memory Map for dsPIC30F6012A/6014A ................... 35
Near Data Space ........................................................ 37
Software Stack ............................................................ 37
Spaces ........................................................................ 33
Width ........................................................................... 36
Erasing ........................................................................ 66
Erasing, Block ............................................................. 66
Erasing, Word ............................................................. 66
Protection Against Spurious Write .............................. 69
Reading....................................................................... 65
Write Verify ................................................................. 69
Writing ......................................................................... 67
Writing, Block .............................................................. 68
Writing, Word .............................................................. 67
Brown-out Reset ............................................... 184, 185
I/O Pin Input Specifications ....................................... 183
I/O Pin Output Specifications .................................... 183
Idle Current (I
Low-Voltage Detect................................................... 183
LVDL ......................................................................... 184
Operating Current (I
Power-Down Current (I
Program and EEPROM............................................. 185
Bit Clock Generator................................................... 129
Buffer Alignment with Data Frames .......................... 131
Buffer Control ............................................................ 125
Buffer Data Alignment ............................................... 125
Buffer Length Control ................................................ 131
COFS Pin.................................................................. 125
CSCK Pin.................................................................. 125
CSDI Pin ................................................................... 125
CSDO Mode Bit ........................................................ 132
CSDO Pin ................................................................. 125
Data Justification Control Bit ..................................... 130
Device Frequencies for Common Codec CSCK Frequen-
Digital Loopback Mode ............................................. 132
Enable....................................................................... 127
Frame Sync Generator ............................................. 127
Frame Sync Mode Control Bits ................................. 127
I/O Pins ..................................................................... 125
Interrupts ................................................................... 132
Introduction ............................................................... 125
Master Frame Sync Operation .................................. 127
Operation .................................................................. 127
Operation During CPU Idle Mode ............................. 132
Operation During CPU Sleep Mode .......................... 132
Receive Slot Enable Bits........................................... 130
Receive Status Bits ................................................... 131
Register Map............................................................. 134
Sample Clock Edge Control Bit................................. 130
Slave Frame Sync Operation .................................... 128
Slot Enable Bits Operation with Frame Sync ............ 130
Slot Status Bits.......................................................... 132
Synchronous Data Transfers .................................... 130
cies (Table) ....................................................... 129
IDLE
) .................................................... 180
DD
)............................................. 179
PD
) ........................................ 181
Development Support ....................................................... 173
Device Configuration
Device Configuration Registers ........................................ 161
Device Overview 3, 11, 17, 27, 41, 47, 53, 59, 65, 71, 75, 81,
Disabling the UART .......................................................... 107
Divide Support .................................................................... 20
DSP Engine ........................................................................ 21
Dual Output Compare Match Mode .................................... 90
E
Electrical Characteristics .................................................. 177
Enabling and Setting Up UART
Enabling the UART ........................................................... 107
Equations
Errata .................................................................................... 9
External Clock Timing Characteristics
External Clock Timing Requirements ............................... 187
External Interrupt Requests ................................................ 51
F
Fast Context Saving ........................................................... 51
Flash Program Memory ...................................................... 53
I
I/O Pin Specifications
Timing Characteristics
Timing Requirements
Transmit Slot Enable Bits ......................................... 130
Transmit Status Bits.................................................. 131
Transmit/Receive Shift Register ............................... 125
Underflow Mode Control Bit...................................... 132
Word Size Selection Bits .......................................... 127
Register Map ............................................................ 163
FBORPOR ................................................................ 161
FBS........................................................................... 161
FGS .......................................................................... 161
FOSC........................................................................ 161
FSS........................................................................... 161
FWDT ....................................................................... 161
85, 89, 93, 97, 105, 113, 125, 135, 165
Instructions (Table) ..................................................... 20
Multiplier ..................................................................... 23
Continuous Pulse Mode.............................................. 90
Single Pulse Mode...................................................... 90
AC............................................................................. 186
DC ............................................................................ 177
Setting Up Data, Parity and Stop Bit Selections ....... 107
ADC Conversion Clock ............................................. 137
Baud Rate................................................................. 109
Bit Clock Frequency.................................................. 129
COFSG Period.......................................................... 127
Serial Clock Rate ...................................................... 102
Time Quantum for Clock Generation ........................ 119
Type A, B and C Timer ............................................. 194
Type A Timer ............................................................ 194
Type B Timer ............................................................ 195
Type C Timer ............................................................ 195
Control Registers ........................................................ 54
AC-Link Mode................................................... 200
Multichannel, I
AC-Link Mode................................................... 200
Multichannel, I
NVMADR ............................................................ 54
NVMADRU ......................................................... 54
NVMCON............................................................ 54
NVMKEY ............................................................ 54
2
2
S Modes................................... 198
S Modes................................... 199
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